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Post-Layout Simulation without front-end files of I/O cells

JavadBa

Hello,

We are using the TSMC 180um for a low power project in our group. Now we are going to do a post-layout simulation for our design. Still, unfortunately, we see that we haven't access to the front-end (Schematics) files of Input/output (IO) cells in IO libraries. I contact by their support in Europractice (Imec). They said we could not access front-end information till tape-out time.  

Is there anyone that has worked by TSMC PDKs and have the same problem? If we cannot access those files cause of some protection issue of TSMC company with university licenses, Please let me know how we can do LVS check or post-layout simulation? 

Best,

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