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Verilog $random seems to be not random

HoWei

Hi,

I want to generate a random number between -1 and 1 in Verilog-A by using "$rdist_uniform" or "$random", but the behaviour is not as I expect it.

My code is something like:

@ ( initial_step ) begin

for (1=0; i<10; i=i+1) begin

   myvar[i]= $rdist_uniform(seed,-1,1)

end

end

When "seed=123" ( a constant) i always get the same value in myvar[0:9].

When "seed=i" the values in myvar[0:9] are increasing linearily.

I am missing the "randomicity" in the values.

If I would need to scramble the seed, I also could use the scrambled value instead of the random function.

How can I generate randomly distributed values ?

  • Okay, I found that (for whatever reason) it works when I place the seed variable outside of the for loop:

    @ ( initial_step ) begin

    seed=32134

    for (1=0; i<10; i=i+1) begin

       myvar[i]= $rdist_uniform(seed,-1,1)

    end

    end

  • in reply to HoWei

    You shouldn't give a new seed every time you call it as that would give a very non-random sequence. The original sequence was indeed random, but it's just that you're starting from a fixed seed (which is usually a good idea for reproducibility of results; it would be very annoying if each time you ran the simulation you got a different answer, as otherwise you couldn't reproduce a previous observation).

    Andrew.

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