I was simulating a VHDL module in AMS with plot in VIVa.
The module looks like as at the end of this post.
If deltat_rec value is same at nth, n+1th rising edge of clock signal 'clk', the wavescan plot ( in SampleHold trace format ) of signal deltat_rec does have a point at nth rsing edge but NOT at n+1th rising edge.
Is there any we can ensure that the WaveScan plot doesn't miss n+1th point so that when we will export the trace, the file will have n+1th point.
deltat_proc:process(clk)beginif (clk='0') and (clk' event) thendeltat_rec <= delta_t;end if;end process deltat_proc;
I think a more complete example will be needed to try this out and advise you (that's partly the reason why I've not answered this so far). I don't have time to spend time putting together a complete example to investigate...
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