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Hierarchical member access in VerilogA

DimitarT

Hi,

 

I need to access a variable of instance from within the parent module in VerilogA. Something like this:

module child;

      integer child_int;
// some code
//....

endmodule

module parent;

     child my_child;

  analog begin
      @(initial_step) 
           $display(“Child_int value : %d”, my_child.child_int);
  end     

endmodule      

 

This example results in the following error during extraction:

Error found by spectre during AHDL compile.

    ERROR (VACOMP-2162): "$display("Child_int value %s", my_child.child_int<<--?

        ); "

        "/home/……./projects/……/veriloga/veriloga.va",

        line 124: Encountered a hierarchical name that is either incomplete or

        unsupported. Specify the hierarchical name as :

        [ instance_name{.instance_name}.]HDL_Instance_name

 

Searching through the Cadence VerilogA LRM doesn’t really give any hint. So what am I missing?

Thanks and best regards,

Dimitar

Parents

  • Hi,

    shortly after posting this question I noticed that in the Cadence VerilogA LRM it is explicitly mentioned that "Named nodes in hierarchical instantiation" are not supported.

    Better late than even later Slight smile

  • in reply to DimitarT

    Actually, I don't think that's what this limitation is talking about (not sure I could find the precise reference you mention anyway).

    However, you can achieve the same thing for variable access using the $cds_get_analog_value function (or $cgav for short):

    $display("Child_int value : %g", $cgav("my_child.child_int"));

    Note that this returns the value as a float even though it's an integer inside, but this does work...

    Regards,

    Andrew.

  • in reply to Andrew Beckett

    Actually I cited from VerilogA LRM version 6.1 from 2006, p.491. 

    Thanks for the suggestion with $cgav(), it works in my setup!

    Best regards,

    Dimitar

Reply Children
  • in reply to DimitarT

    Hi Dimitar,

    I'm not sure why you'd use such an ancient version of the VerilogA reference manual. There have been 14 major releases since then. I did find some copies on the internet (which are breaking copyright by publishing) so maybe that's why you're looking at an old manual rather than the one in your installation... (I hope you're not using MMSIM6.1!)

    Anyway, glad $cgav works (I'm sure you're not using a 14-year old software version because of that!)

    Andrew.

  • in reply to Andrew Beckett

    Hi Andrew,

    strangely enough, this 2006' LRM is the first web search result I get :) Apologies for the confusion.

    But yes, I forgot to mention I used IC 6.1.8/ spectre18.10/mmsim15.10.

    Thanks for the help!

    -

    Dimitar

  • in reply to DimitarT

    Thanks Dimitar - I found that University re-published document too. Our documentation is not supposed to be re-published by anyone for two reasons:

    1. It's Cadence's copyright and so they are not allowed to publish it (page 2 of most of our manuals say this, including this one).
    2. It tends to lead to people consulting out of date information (as you were doing - in current versions the Named nodes in hierarchical instantiation is no longer in that section of the documentation; anyway, what you are doing here is not a hierarchical instantiation so whatever that is referring to is not relevant here). I think it's the next bullet point, Hierarchical names except for node.potential.abstol, although that is rather vague because hierarchical node names in the V() function do work for hierarchical node names. So it's not terribly well worded.

    Anyway, thanks for the pointer. I'd suggest you run (in the terminal):

    `spectre_root`/bin/cdnshelp

    Or look at the doc directory under the location that "spectre_root" returns, and then at veriaref/veriaref.pdf which gives you the current version. BTW, having both SPECTRE and MMSIM in your path makes no sense sense SPECTRE is just the newer name for the release and SPECTRE18.10 is a 3-year newer version than MMSIM15.10

    Regards,

     Andrew.

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