How to add an accurate triggered clock in a testbench

This ought to be possible with VerilogA and I see no reason why a properly written model should not be accurate. Perhaps you should post  your model and an example which shows the problem you're seeing?

It's not 100% clear what behaviour you want here, to be honest.

Andrew

Dear Andrew,

If you see the attached snapshot below, I want to trigger the clock (the green plot) at the fifth rising edge of data input ( the white plot).

So, I have a counter which counts the rising edges of data input and generates the trigger (the red plot).

I use phase= idt(1,0,reset) for phase integration (please see the VerilogA code below). The cyano color plot is the phase plot.  From the plot it is apparent that the clock is not accurate. Its pulse width is varying and so is its period.

Could you please have a look and tell where I am going wrong.

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// VerilogA for VERILOG_A_MODEL_2, sample_clk_centre, veriloga

`include "constants.vams"
`include "disciplines.vams"

module sample_clk_centre(data_in,trigger,clk_out,phase_out);
input data_in;
output clk_out, phase_out,trigger;
electrical data_in, clk_out,phase_out,trigger;
parameter real Vlo=0, Vhi=1.25;
parameter real Vth=0;
parameter integer clk_count=4 from [2:inf);
parameter integer dir=1 from [-1:1] exclude 0;
parameter integer count_no=5;

// dir=1 for positive edge trigger
// dir=-1 for negative edge trigger
parameter real ttol=0.5p;
parameter real vtol=0.5p;
parameter real tt = 1p;

parameter real tdel = 0;
parameter real trise = 1e-15;
parameter real tfall = 1e-15;
parameter real UI = 30e-12;

integer count, count_en, counte_e, n, seed;
real delay_t ,T_period;
real phase,reset;
real integrand;
real trigger_en;

analog begin

@(initial_step) begin
V(clk_out) <+ 0;
delay_t= 100n;
count_en=1;
count=0;
reset =0;
n=-1;
T_period=UI;
trigger_en=0;
end

phase= idt(1,0,reset) - delay_t ; // Phase Integration
reset =0;
//phase= idtmod(integrand,0,1,0);

@(cross(V(data_in) - Vth, dir)) begin
// count input transitions
if (count_en == 1) begin
count = count + 1;
end
end

if (count >= count_no) begin
count_en = 0;
count=0;
trigger_en=1;
delay_t =0;
reset=1;
end

@(cross(phase-(T_period-1p),+1,ttol,vtol)) begin
reset=1;
end

n= (phase >=0) && (phase < (UI/2));
//end

V(clk_out) <+ transition(n ? Vhi:Vlo,0,tt);
V(phase_out) <+ phase ;
V(trigger) <+ trigger_en;

end
endmodule

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It probably would make more sense to use @(timer...) to determine the pulse width and edges after your clock is started from the trigger point (using @(cross..)), rather than integrating and then having a crossing point on the integrated phase.

I don't have time to write the Verilog-A and test it, but hopefully that will give you a pointer in the right direction.

Andrew.