How to reduce parasitics from layout

 Dear  jyoti,  

  How to reduce parasitics from layout? When i simulate pre-layout and post-layout form of my design there is vast variation in delay and power when i measure. how can I improve my layout design?  

As a start, have you examined the parasitic capacitances on your circuit nodes from an extracted view of your layout? This can be done from your schematic in Virtuoso using the following:

 Launch->Plug-ins->Parasitics  

 This will add a menu to your Virtuoso window “Parasitics”. From that new menu, select Setup. From the resulting dialog box, you can choose your extracted view and either annotate the nodes of your schematic with the layout based capacitances or display/write all the capacitances to a file. This will provide some information to use in creating a version of your schematic netlist based simulation with layout parasitics included. You may still need to include trace resistances or power/ground impedance, but this will provide a starting point for your correlation effort. This will provide some guidance as to how your layout can be improved.  

 I hope this helps.  

 Shawn