From ideal switch to CMOS transitor switch

Hello Jaikrishnan,

An ideal switch has zero on resistance and infinite off resistance, but of course we do not live in an ideal world.

To understand the switch performance, you should simulate your switch for the worst case conditions. The worst case condition is achieved: 

1. By making VDS=0 and then the VGS=Vclk-VIN 

2. Making the off resistance very large.

These conditions will allow you to choose the transistor W/L ratio.

I would start with a simulation of NMOS switch by modeling the NFET as a resistor and see how it is transferring charges to the Capacitor. If you are satisfied with the performance, you can use the resistance to model your NFET size. Ron=1/Knp.W/L(Vgs-Vth).

There are some excellent Analog Textbooks on how to go about doing this. I would refer to CMOS Analog Circuit design by Phillip Allen and Douglas Holberg chapter 4. https://www.abebooks.com/9780199937424/CMOS-Analog-Circuit-Design-Phillip-0199937427/plp
I hope that helps. 

Dear Jaikrishnan,

Jaikrishnan said:

But what other factors should I need to consider to exactly replicate the behavour given by the ideal switch (of course it will no longer be an ideal switch when it is implemented using transistor)

How about the width and length of the transsitor used (if it is an NMOS or PMOS based transistor).

How should I come up with how much Ugs I need to supply?

If I may, in addition to wgtkan's excellent directions and recommendations, I might provide a couple of additional considerations...

1. The behavior of the analogLib ideal switch is independent of the voltages on either its input or output terminals. The switch input and output terminals are exclusively a function of the value of its controlling terminal voltage. In essence, its input and output terminal impedances are not in any way determined by how the voltages on either of its input and output terminals vary. When converting an ideal switch to an MOS based switch, the input and output terminal impedances will directly vary as the voltage on not only the analog voltage at its gate, but the transistor drain and source terminals as well. You have not indicated how the voltages at the input and output terminals of your ideal switch vary relative to its controlling terminal - but this is also something to consider. Specifically, if the voltage at either the source or drain of your proposed NMOS or PMOS device approaches the "on voltage" of your NMOS or PMOS gate terminal, the impedance of the NMOS or PMOS switch will become extremely large - totally unlike the behavior of the ideal switch. Just increasing the W/L of the NMOS or PMOS device will not eliminate this issue. To avoid this problem, a more general and "safer" means of implementing a CMOS based switch is provided in Figure 1. This topology will show a switch impedance real part that varies with drain or source voltage as shown in the blue curve of Figure 1. An implementation with only a single MOS or PMOS device will show a terminal real impedance as shown in the red curve of Figure 1.

2. Also shown in Figure 1 are capacitances between the switching terminals and the input and output terminals. This will lead to charge injection to the input and output terminals when the switch terminals undergo a transition. Increasing device W/L to reduce the switch real impedance will only increase the value of these capacitors and the amount of charge injected. Hence, there is a trade-off between the maximum device W/L ti minimize switch real impedance and minimum W/L to minimize charge injection.

3. As you may notice, sometimes what looks to be a very simple device topology often requires a lot more study than expected. Unfortunately, what looks to be a simple MOS implementation of an ideal switch is one of those cases! I hope that wgtan's excellent suggestions and these addition comments provide you some help!

Shawn

Thank you wgtkan. I will refer those any try the simulations

Thank you Shawn for your additional information. I will verify these