noise/jitter transfer function along clock-driven inverter chain

Of course the sampled noise can decrease along the chain if the signal slope increases. There isn't anything strange about this as long as the resulting jitter does not decrease. The output noise is not "incorrect" because of this and the noise summary of the sampled noise correctly shows the devices that contribute to the jitter.

Sidebands don't make much sense in a sampled pnoise analysis; they simply give you a shifted version of the original result at sideband 0 (and in that result, the noise at 15G-30G is just a mirror image of the noise at 0-15G).

Sampled PXF or sampled PAC is the right way to examine the transfer functions. You can also try the parameter separatenoise=yes (I have never really used it), but this won't work if you also use pnoisemethod=fullspectrum.

I suggest that you also examine the jitter caused by power supply variations with a sampled PXF (or sampled PAC) analysis.

Hi Frank,

Frank Wiedmann said:

Of course the sampled noise can decrease along the chain if the signal slope increases.

to avoid any doubt I did the following simulation. I created an ideal inverter using the switch element from analogLib that gives a very steep response and I checked what happened at its output.
The slope is then largely increased from N4 to this new output, but the noise is not decreasing, but largely increasing.
In this very simplified situation, since noise contributor is only the input inverter, the jitter must be constant after the first inverter. In other words, the ratio between integrated noise over slope must be constant. When the ideal inverter is introduced, since the slope tends to infinity, the noise too must go to infinity to keep the ratio (i.e. the jitter) a constant.

Frank Wiedmann said:

Sidebands don't make much sense in a sampled pnoise analysis; they simply give you a shifted version of the original result at sideband 0 (and in that result, the noise at 15G-30G is just a mirror image of the noise at 0-15G).

I agree that noise seen at the output node at every other bandwidths like 15-30, 30-45, 45-60 etc... will be the same as the one you get in 0-15G.
However, the number of sidebands that we are talking about are the folded ones, that you can choose in the pnoise form. Every high-frequency bandwidth will contribute to the 0-15G bandwidth noise.
In this simplified simulation I chose to keep 2 bandwidths only contributing to the ouput noise.

You are absolutely right; I obviously was a little too quick with my response.

Of course I should have written "the sampled noise can decrease along the chain if the signal slope decreases". Jitter (in s) is sampled noise (in V) divided by signal slope (in V/s), so for constant jitter, the sampled noise will decrease or increase at the same ratio as the signal slope, as you correctly remarked. The average noise over the signal period will of course not decrease; if you have a lower slope, the noise due to jitter will be present over a larger part of the period.

I also mixed up the sidebands parameter with the relharmnum parameter (because I usually use the maxsideband and not the sidebands parameter). Relative frequency sweeps that can be specified with relharmnum don't make much sense for sampled pnoise because they will only give you a shifted version of the original result. However, as you correctly remarked, the sidebands parameter specifies the sidebands in which the noise will be taken into account for calculating the result. The numbering of the sidebands by SpectreRF is not always very intuitive, but  [-1 1] indeed corresponds to 15G-30G (or rather -30G - -15G) and 30G-45G as you said (while sideband 0 is 0G-15G).

Yes, Frank, I agree with you.
Rethinking about my previous results and after this discussion, there is still a thing that I don't understand: if in the inverter chain (with MOS inverters) the only noisy element is the first inverter, the jitter should be constant along the chain. Is it correct?
In my simulation, however, I see the jitter increasing from ~40f to ~47f (using only 2 sidebands in the pnoise form) and it does seem strange. If instead I select up to 20 sidebands, I see the jitter decreasing from the AC coupler output to the second inverter output, and then increasing again.
I believe there is something strange going on.

I would recommend using a large number of sidebands (or preferably the pnoisemethod=fullspectrum parameter, which is much more efficient) in order to avoid simulation artifacts. Lowpass filtering in or between the inverter stages might perhaps cause the jitter to decrease. And please don't forget to also look at the influence of power supply variations, which might well be dominant over the effect of random noise.

Right now I'm trying different configurations of the pss/pnoise and wanted to share the results with you and ask your opinion.
N1...N4 are the voltage nodes where I measure the jitter. Remember that the only noisy element is the first inverter.
Up to now I used pss with 10 harmonics and in pnoise I selected 2 sidebands from "select from a range" that gives jitter increasing from 40f.

Seeing these results I increased the number of PSS harmonics to 100 to see what happened. The thing that surprise me more is the comparison fullspectrum vs default.

Your results seem to confirm my idea that the decreasing jitter is caused by low-pass filtering. The resistor is in parallel to the first inverter and produces noise over a very large bandwith at N1. This noise is then low-pass filtered in the second inverter, which reduces the integrated noise and with it also the total jitter. The bandwidth of the resistor noise in your simulation setup seems to be extremely large, as there is still a difference between maxsideband=100 and pnoisemethod=fullspectrum (with a PSS fundamental of 30G).

With pnoisemethod=fullspectrum, you take into account the white noise in the entire bandwidth of the simulation setup; this bandwidth can be set for example with the PSS parameter maxacfreq or with the number of harmonics in the PSS analysis (see https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nTk7EAE for details). This is the reason why you see a difference between the simulations with 10 and 100 PSS harmonics. The maxsideband parameter does not make any difference for your circuit for pnoisemethod=fullspectrum, because it is only used for colored noise (like 1/f noise) in this case. With pnoisemethod=default and maxsideband=2, you simply neglect a lot of the noise in your circuit, especially at N1 (and even more so for sidebands=[-1 1]).

I am not quite sure what causes the slight increase in jitter from N2 to N4, but looking at the noise summaries at these points might give you more insight on this.

Your results seem to confirm my idea that the decreasing jitter is caused by low-pass filtering. The resistor is in parallel to the first inverter and produces noise over a very large bandwith at N1. This noise is then low-pass filtered in the second inverter, which reduces the integrated noise and with it also the total jitter. The bandwidth of the resistor noise in your simulation setup seems to be extremely large, as there is still a difference between maxsideband=100 and pnoisemethod=fullspectrum (with a PSS fundamental of 30G).

With pnoisemethod=fullspectrum, you take into account the white noise in the entire bandwidth of the simulation setup; this bandwidth can be set for example with the PSS parameter maxacfreq or with the number of harmonics in the PSS analysis (see https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nTk7EAE for details). This is the reason why you see a difference between the simulations with 10 and 100 PSS harmonics. The maxsideband parameter does not make any difference for your circuit for pnoisemethod=fullspectrum, because it is only used for colored noise (like 1/f noise) in this case. With pnoisemethod=default and maxsideband=2, you simply neglect a lot of the noise in your circuit, especially at N1 (and even more so for sidebands=[-1 1]).

I am not quite sure what causes the slight increase in jitter from N2 to N4, but looking at the noise summaries at these points might give you more insight on this.

 Dear Frank and nicodena,

I have been studying the noise in a series of coupled inverters for some time using the sampled phase noise option. As I mentioned, I filed a case  with Cadence as the analysis in many cases does not provide intuitive results. For example, as nicodena noted, some nodes in the chain show unexpected increases in noise by very large amounts followed by a node where the noise drops much more than can be expected due to filtering (and evident in the spectral plots). I also found that the noise often shows a marked increase at one or two temperatures when I sweep the temperature values. Like you, I varied multiple settings trying to explain the results and ultimately resorted to opening a case with Cafence to help resolve the issue - or as I also mentioned - correct my use of the tool!

Shawn 

Hi Frank, hi Shawn, actually the resistor is not noisy, the only noisy element is the first inverter. 
To check your suggestion about noise-filtering I tried to remove the x12 inverter attached to N2: in this way N2 slope increases since the second inverter is auto loaded. However, the overall noise results are practically unchanged (changes are below 0.5fs over a jitter of ~50fs) and the decrease between N1 and N2 still remains equal.

I'll try to summarize the problems that are still open (for me) after our discussion, maybe also Shawn has the same doubts:

1) testbench: 30GHz clock-driven inverter chain, with an AC coupler as input stage and its inverter is only noisy element; pss+pnoise simulation, where pss harmonics=100 and pnoise sidebands is "fullspectrum"; jitter over 10k-15GHz is decreasing from N1 to N2 and then slightly increasing toward N4. The expected behavior was that the jitter remains constant from N1 to N2, since the only contributor is the first inverter in the AC coupler.

2) if I'd like to check the noise transfer function, what simulation should I perform? For example, if I perform a PXF keeping the N2 as output node and using the sampled option with the same signal as trigger, how should I interpret the results? Unfortunately I can't upload screenshot anymore. I'd expect that the "gain" at 30GHz would be the gain that i see in the PSS spectrum @30GHzfrom N1 to N2, but it is not like this. What kind of "gain" is the one in 30GHz? And the one in 0Hz? This is not clear to me in this kind of simulation.

3) PAC and PXF simulation don't agree, even if they should. 
PAC and PXF setup is:
             pac ( N2 0 ) pac crossingdirection=all
            + thresholdvalue=0.45 ptvtype=sampled sweeptype=absolute start=15G
            + stop=30G lin=30 sidebands=[-3 -2 -1 0 1 2 3] annotate=status

           pxf ( N2 0 N2 0 ) pxf
           + crossingdirection=all thresholdvalue=0.45 ptvtype=sampled
           + sweeptype=absolute start=15G stop=30G lin=30 sidebands=[-3 -2 -1
           + 0 1 2 3] annotate=status stimuli=nodes_and_terminals

PAC adn PXF results are plot as "voltage gain" between the two nodes.
Please let me know if you have more suggestions. Thanks a lot everyone.

Nicola

I suggest that you contact Cadence Support (as Andrew and Shawn already suggested) and let them sort it out. The results that you presented yesterday looked consistent between each other, but there is probably either something wrong in your simulation setup or the simulator is having problems. Without direct access to the testcase, this is very difficult to debug.