noise/jitter transfer function along clock-driven inverter chain

Dear Nicola,

nicodega said:

So here's my questions:
1) how is that possible that noise is decreasing along the chain?

I have experienced the similar non-intuitive results using a pss/pnoise (sampled jitter) analysis of a number of circuit topologies very similar to the schematic you describe. I have opened a case with Cadence to better understand the non-intuitive results and am currently working with one of their very best Application Engineers to resolve the issue - or at least understand my incorrect use of the new tool!

Shawn

I too would suggest opening a case with customer support. My guess is that what you're seeing is related to the different edge speeds at the different nodes, but it's quite hard to tell from just pictures - I would want to look more closely at the data.

Regards,

Andrew.

Hi Shawn, hi Andrew,

thank you for your answers. I'll go through the local customer support.
Yes, Andrew, my guess is the same: jitter is correctly calculated and it  is slightly increasing along the chain, it can't decrease even if at the end the inverter has ideal transitions (infinite slope). But then to extrapolate the output noise at each node it takes the local slopes into account and in N4 the slope is worst than in node N3.
In fact, i checked that the ratio between the rising slopes at N3 and N4 and the low-frequency output noise at the same nodes: it's the same.

This stated, I'm not sure I'll be able, in a simulation with all contributors and sidebands, to extract the correct contributors to jitter at the output of a chain since I usually calculate them through the noise summary, that is equal to the incorrect Ouput Noise spectrum that I plotted above.

Shawn, please let me know if you have updates on your side!

Thank you
Nicola

Of course the sampled noise can decrease along the chain if the signal slope increases. There isn't anything strange about this as long as the resulting jitter does not decrease. The output noise is not "incorrect" because of this and the noise summary of the sampled noise correctly shows the devices that contribute to the jitter.

Sidebands don't make much sense in a sampled pnoise analysis; they simply give you a shifted version of the original result at sideband 0 (and in that result, the noise at 15G-30G is just a mirror image of the noise at 0-15G).

Sampled PXF or sampled PAC is the right way to examine the transfer functions. You can also try the parameter separatenoise=yes (I have never really used it), but this won't work if you also use pnoisemethod=fullspectrum.

I suggest that you also examine the jitter caused by power supply variations with a sampled PXF (or sampled PAC) analysis.

Hi Frank,

Frank Wiedmann said:

Of course the sampled noise can decrease along the chain if the signal slope increases.

to avoid any doubt I did the following simulation. I created an ideal inverter using the switch element from analogLib that gives a very steep response and I checked what happened at its output.
The slope is then largely increased from N4 to this new output, but the noise is not decreasing, but largely increasing.
In this very simplified situation, since noise contributor is only the input inverter, the jitter must be constant after the first inverter. In other words, the ratio between integrated noise over slope must be constant. When the ideal inverter is introduced, since the slope tends to infinity, the noise too must go to infinity to keep the ratio (i.e. the jitter) a constant.

Frank Wiedmann said:

Sidebands don't make much sense in a sampled pnoise analysis; they simply give you a shifted version of the original result at sideband 0 (and in that result, the noise at 15G-30G is just a mirror image of the noise at 0-15G).

I agree that noise seen at the output node at every other bandwidths like 15-30, 30-45, 45-60 etc... will be the same as the one you get in 0-15G.
However, the number of sidebands that we are talking about are the folded ones, that you can choose in the pnoise form. Every high-frequency bandwidth will contribute to the 0-15G bandwidth noise.
In this simplified simulation I chose to keep 2 bandwidths only contributing to the ouput noise.

You are absolutely right; I obviously was a little too quick with my response.

Of course I should have written "the sampled noise can decrease along the chain if the signal slope decreases". Jitter (in s) is sampled noise (in V) divided by signal slope (in V/s), so for constant jitter, the sampled noise will decrease or increase at the same ratio as the signal slope, as you correctly remarked. The average noise over the signal period will of course not decrease; if you have a lower slope, the noise due to jitter will be present over a larger part of the period.

I also mixed up the sidebands parameter with the relharmnum parameter (because I usually use the maxsideband and not the sidebands parameter). Relative frequency sweeps that can be specified with relharmnum don't make much sense for sampled pnoise because they will only give you a shifted version of the original result. However, as you correctly remarked, the sidebands parameter specifies the sidebands in which the noise will be taken into account for calculating the result. The numbering of the sidebands by SpectreRF is not always very intuitive, but  [-1 1] indeed corresponds to 15G-30G (or rather -30G - -15G) and 30G-45G as you said (while sideband 0 is 0G-15G).

Yes, Frank, I agree with you.
Rethinking about my previous results and after this discussion, there is still a thing that I don't understand: if in the inverter chain (with MOS inverters) the only noisy element is the first inverter, the jitter should be constant along the chain. Is it correct?
In my simulation, however, I see the jitter increasing from ~40f to ~47f (using only 2 sidebands in the pnoise form) and it does seem strange. If instead I select up to 20 sidebands, I see the jitter decreasing from the AC coupler output to the second inverter output, and then increasing again.
I believe there is something strange going on.

I would recommend using a large number of sidebands (or preferably the pnoisemethod=fullspectrum parameter, which is much more efficient) in order to avoid simulation artifacts. Lowpass filtering in or between the inverter stages might perhaps cause the jitter to decrease. And please don't forget to also look at the influence of power supply variations, which might well be dominant over the effect of random noise.

Right now I'm trying different configurations of the pss/pnoise and wanted to share the results with you and ask your opinion.
N1...N4 are the voltage nodes where I measure the jitter. Remember that the only noisy element is the first inverter.
Up to now I used pss with 10 harmonics and in pnoise I selected 2 sidebands from "select from a range" that gives jitter increasing from 40f.

Seeing these results I increased the number of PSS harmonics to 100 to see what happened. The thing that surprise me more is the comparison fullspectrum vs default.

Your results seem to confirm my idea that the decreasing jitter is caused by low-pass filtering. The resistor is in parallel to the first inverter and produces noise over a very large bandwith at N1. This noise is then low-pass filtered in the second inverter, which reduces the integrated noise and with it also the total jitter. The bandwidth of the resistor noise in your simulation setup seems to be extremely large, as there is still a difference between maxsideband=100 and pnoisemethod=fullspectrum (with a PSS fundamental of 30G).

With pnoisemethod=fullspectrum, you take into account the white noise in the entire bandwidth of the simulation setup; this bandwidth can be set for example with the PSS parameter maxacfreq or with the number of harmonics in the PSS analysis (see https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nTk7EAE for details). This is the reason why you see a difference between the simulations with 10 and 100 PSS harmonics. The maxsideband parameter does not make any difference for your circuit for pnoisemethod=fullspectrum, because it is only used for colored noise (like 1/f noise) in this case. With pnoisemethod=default and maxsideband=2, you simply neglect a lot of the noise in your circuit, especially at N1 (and even more so for sidebands=[-1 1]).

I am not quite sure what causes the slight increase in jitter from N2 to N4, but looking at the noise summaries at these points might give you more insight on this.