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Stability check issue during phase starting with 0 degree

Hi!

I'm trying to design buffer amp for specific application, so I want to check stability such as phase margin using an instance 'iprobe'(actually it doesn't matter to use ac simulation). However, the loop gain phase plot of the circuit starts with 0 instead of 180 deg and it's unexpected plot. I think it could be related with positive feedback or multi loops, but I'm not sure about it. The transient result of the circuit works well, but I want to check the figure of phase. Could you please help me? How can I make it clear?

Thanks.

Frank Wiedmann over 5 years ago

You are giving very little detail, so it's hard to guess the cause for this behavior in your case. A plot of the loop gain results and the schematics would certainly help. You can take a look at https://designers-guide.org/forum/YaBB.pl?num=1294178255; this thread covers one possible reason for such a behavior.
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MIN KIM over 5 years ago in reply to Frank Wiedmann

Thank you for your answer. Actually I think it's similar with my case, but I can't find vprobe in cadence. Then it's only one way to check the stability is using Nyquist stability criterion, if I want to know specific figure of phase margin? Is it right?
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Frank Wiedmann over 5 years ago in reply to MIN KIM

In my example circuit, Vprobe is an ideal voltage source with 0 V that is used as the probe in the stb analysis. You can also use a current probe (iprobe) for this purpose. If your results look like the ones in my example, you can probably simply ignore the behavior of the loop gain at low frequencies and calculate the phase margin in the usual way after cutting off the low-frequency results.
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