DSPF file disregard in extracted simulation

I wouldn't advise using stitching; whilst spectre supports this, we've deemphasised it because it's hard to get stitching complete (as you're seeing).

The best approach is to specify the DSPF file via the Setup->Simulation Files->DSPF, but to ensure that the config (if using the hierarchy editor) does include the schematic view of the cell you're annotating. The reason being is that then the netlist contains a subckt definition of the block for which you have DSPF, and it then ties up the terminals between the schematic subckt and the terminals of the subckt in the DSPF. This is beneficial because it means that you don't have to worry about the port order in the DSPF - the instance of the block in the netlist will match the order of the terminals in the schematic subckt, but it will actually use the DSPF subckt contents.

If you use spf= then that's for DSPF stitching, which is not what you want to use here.

Regards,

Andrew.

HI Andrew,

Thanks for your answer. Originally I was using the Setup->Simulation Files->DSPF way, but it did not seem to be effective for the given circuit, since there was no change in the output. I also got the warning

Warning from spectre during circuit read-in.   
WARNING (SFE-2957): No schematic subckt definition is available, spf port order is used.

I've not using the hierarchy editor, but schematic had to be in the switch view list.

What is the advisable way to set up the extracted netlist for post-layout simulations? Is it the mentioned Setup->Simulation Files->DSPF? In my previous job there were high level wrappers written by the company to set up everything, but now I do not have that luxury and I have to set up everything. I know how to edit the netlist with a text editor to add a parasitic spectre netlist, but there must be a more straightforward way from the graphical interface. The simplest seems to me to create a new, extracted cellview, but I do not know how to create that from the extracted netlist, without creating a new cell.

In what document can I find more explanation about the different ways and their benefits and drawbacks? In the ADE L User Guide I've only found description how to use the Simulation Files window, but no description about the methods, or what will be exactly done by the simulator in a way what could help me.I would rather consult the documentation than asking in the forum, but often I not able to manage the information by myself.

Thanks,
Zoltan

Dear Zoltan,

To use the DSPF view of a sub circuit, as you discovered,

1. Select the schematic view in either the Hierarchy editor or in the switch view list of ADE-L

2. Provide a pointer to the DSPF file in the ADE-L menu item Setup->Simulation Files GUI. In that panel, check the use of the DSPF file and provide the path to the file.

What this will do is create a schematic view based netlist with an include statement which will provide the path to your DSPF file. Spectre will recognize the DSPF include file and utilize that view in the simulation. (You may want to view the resulting netlist, called input.scs, in the netlist directory just to see this.)

You could choose a different view than the schematic view in your switch list - but this will only increase the time for netlisting. Hence, choosing the schematic view minimizes the time to create a netlist.

Does this help at all Zoltan? I hope I understood your questions.

Shawn

I suspect the problem you are seeing, Zoltan, is because the subckt name in the netlist doesn't match the subckt name in the DSPF file. Please post the subckt definition of the block (just the lines defining the subckt and ports) from the input.scs, and the subckt definition lines from the DSPF.

Maybe the Spectre netlister is mapping the name for some reason (maybe it contains an illegal character for spectre?) and it no longer matches the DSPF?

By default the match is case insensitive (that can be controlled via the options when you do the DSPF include, so maybe you've made it case sensitive?)

Regards,

Andrew.

Hi Shawn,

Thanks for taking the time to reply, but unfortunately this was the exact flow, what I have used.

Thanks, Zoltan

Zoltan,

Please see what I said after Shawn's reply...

Andrew

Update: I've just rerun the simulation and now the DSPF had an effect. I have to look at it again, but I have no time at the moment. I will let you know when I can reproduce the issue again or if I will have any conclusions.
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Hi Andrew,

At the time I had no access to the design, but I was intended to look into it.

DSPF definition:

.subckt vco_core_wo_ind VSS VDD Iref_osc vbp Vtune vbn tank_p tank_n outp outn

SCS definition:

subckt vco_core_wo_ind Iref_osc VDD VSS Vtune outn outp tank_n tank_p vbn \
vbp

The pins are the same, just in different order, and the only strange character is the underscore.