Input Capacitance Measurements of Digital Cells in Cadence Liberate

Hi Anuradha,

Capacitance is calculated based on the current through the net and the change in voltage over the same period of time. Please run the saved deck and check the current waveform to see if a large current flows through the pin(s). I suspect you have a large current between A/B when the two pins are at different states.

Regards,

Guangjun

Hi, btw I forgot to mention that the cell also includes an inverter to generate the complement of input C (The cell is self-contained). So basically, there shouldn't be any direct path between input A and B in any state. However I am bit skeptical about the accuracy of the CCS modeling of these type of cells (no separate CCS stages). I use following settings in my script:

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### Input waveform ###
set_var predriver_waveform 2 ;# 2=use pre-driver waveform

### Capacitance ###
set_var min_capacitance_for_outputs 1 ;# write min_capacitance attribute for output pins

### Leakage ###
set_var max_leakage_vector [expr 2**10]
set_var leakage_float_internal_supply 0 ;# get worst case leakage for power switch cells when off
set_var reset_negative_leakage_power 1 ;# convert negative leakage current to 0

### Power ###
set_var voltage_map 1 ;# create pg_pin groups, related_power_pin / related_ground_pin
set_var pin_based_power 0 ;# 0=based on VDD only; 1=power based on VDD and VSS (default);
set_var power_combinational_include_output 0 ;# do not include output pins in when conditions for combinational cells

set_var force_default_group 1
set_default_group -criteria {power avg} ;# use average for default power group

set_var subtract_hidden_power 2 ;# 1=subtract hidden power for all cells
set_var subtract_hidden_power_use_default 3 ;# 3=subtract hidden power from matched when condition then default group
set_var power_multi_output_binning_mode 1 ;# binning for multi-output cell considered for both timing and power arcs
set_var power_minimize_switching 1
set_var max_hidden_vector

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Use of "predriver_waveform 2" is recommended for better CCS accuracy, but does it makes sense for the cells which do not have input buffering (like in my case) ?

Thanks 

Anuradha

Hi,

Please do a Spectre simulation on the saved decks for capacitance. Then plot the current and voltage waveform and A and B. Large capacitance value can be due to large current, which can be very common when the input is NOT connected to the gate of a MOSFET. 

predriver_waveform=2 produce a non-linear waveform that is more realistic, particularly near power/ground levels that are very important for accuracy of CCS models. 

Guangjun   

Dear Guangjun,

Can I confirm one thing ? When signal A and B are connected to the gates of MOSFETs, there is an internal power contribution from A and B through VDD. Since input A and B in this case, do not have VDD/VSS power groups (as they are driven by the pre-driver) they themselves do not contribute to the internal power dissipation (only the switching power due to output load exists). In that case, is my power configuration correct ? 

Kindly clarify....

Hi,

Please confirm if you have checked the waveform for capacitance characterization. We should close the original question first.

For power characterization, the power due to transition of pin/related pin is always counted. It is not what drives the pins that mater. It is current flow inside the cell that maters, due to the input transition . However, you can control whether contribution by side pins is included, using power_add_input_pin.

Regards,

Guangjun

This issue has been resolved by setting appropriate measure_cap_lower/upper_rise/fall tolerances. 

Good. Thanks for updating.

You can always change these threshold to get a different number. If you have seen a large current (which you have never confirmed), then change the threshold may exclude such current.

I am not sure, in your case, this is a solution or just a way to avoid 'unexpected' values. Very often, as design issue can be buried by some a workaround.  

Hi Guang, 

In the case when the drain/source (instead of gate) of the transistor is directly connected to the input, as you know, the miller effect impacts the effective input capacitance. If any of the devices in linear region, the resulting capacitance is the miller capacitance which is larger and indeed draws a larger current. However this rarely happens during the on-off period of the device. So that the measurement slew/cap tolerances have to be set appropriately.  

Thanks for your hints

Anuradha

Hi Guang, 

In the case when the drain/source (instead of gate) of the transistor is directly connected to the input, as you know, the miller effect impacts the effective input capacitance. If any of the devices in linear region, the resulting capacitance is the miller capacitance which is larger and indeed draws a larger current. However this rarely happens during the on-off period of the device. So that the measurement slew/cap tolerances have to be set appropriately.  

Thanks for your hints

Anuradha