Negative Power Numbers During the Synthesis Over a Custom Cell Library (Liberate)

Hi,

I have a requirement to characterize a set of standard cells of following type : 

All of these custom cells have the same transistor arrangement, i.e. a transmission gate pair followed by an inverter. Since the inverter isolates the inputs from the loads of the cell, this cell can be characterized over a wider slew/load range. (i.e. "Liberate - Characterization Setup for Special Mux Cells" RAK (i.e. MXIUI2X1)) .

When a design is synthesized over this custom cell library, the default power reported during the synthesis becomes negative :

i.e. 

However the power report based on the switching activity shows positive power numbers. Moreover for the library of standard CMOS type of cells (both inputs and outputs are buffered) using the same liberate settings, this is not observable ! I use following power calculation settings in the .tcl script : 

#----------------------------------------------- Power -----------------------------------------------------------------------------------------------
### Leakage ###
set_var max_leakage_vector [expr 2**10]
set_var leakage_float_internal_supply 0 ;# get worst case leakage for power switch cells when off
set_var reset_negative_leakage_power 1 ;# convert negative leakage current to 0

### Power ###
set_var voltage_map 1 ;# create pg_pin groups, related_power_pin / related_ground_pin
set_var pin_based_power 0 ;# 0=based on VDD only; 1=power based on VDD and VSS (default);
set_var power_combinational_include_output 0 ;# do not include output pins in when conditions for combinational cells

set_var force_default_group 1
set_default_group -criteria {power avg} ;# use average for default power group

#set_var power_subtract_leakage 4 ;# use 4 for cells with exhaustive leakage states.
set_var subtract_hidden_power 2 ;# 1=subtract hidden power for all cells
set_var subtract_hidden_power_use_default 3 ;# 3=subtract hidden power from matched when condition then default group
set_var power_multi_output_binning_mode 1 ;# binning for multi-output cell considered for both timing and power arcs
set_var power_minimize_switching 1
set_var max_hidden_vector [expr 2**10]
#------------------------------------------------------------------------------------------------------------------------------------------------------------------

What could be the reason for the negative power numbers ?

Thanks in advance

Anuradha