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How do make the clock 25% duty cycle with jitter capability

cADEUser

How do make the clock 25% duty cycle. I am looking for creating 25% duty cycle ( or a certain High pulse width ) clock where I can add random and deterministic jitter. 

Hi Andrew,

My apology for not starting a new thread and just replying to an really old thread with the above question. Here I am starting a new thread on this. 

Your Answer on this :

In this case I'd suggest you use a "bit" source (the Source Type being bit):

It's not quite working. Here's what I have used : 

Since the fall edge sloe is not modified, you get a distorted waveform. How do we fix it ?

Parents

  • Two things:

    1. You've set the rise time not the rise delay, which is why this is not working as I showed it
    2. You've used the vbit component rather than vsource component. For some reason (an oversight) the rise delay and fall delay parameters were not added to the vbit component, so you will need to use vsource instead. Not sure why you did that given that I showed a vsource in my example.

    Note that I checked, and these parameters were added in IC6.1.6 ISR9 (6.1.6.500.9) and in MMSIM13.1 ISR9 - so have been there for some time.

    Regards,

    Andrew.

  • in reply to Andrew Beckett

    Thanks Andrew. It's working fine now.  I was using vbit in my TB for other purpose and thought it would be the same as vsource with pattern=bit. It looks like vbit does not have the rise delay and I ended up mistakenly put that formula in rise time.  I changed to vsource with pattern=bit and put that it rise delay and it's working fine. Thanks a lot for your help. 

    Waveform with the fix : 

  • in reply to cADEUser

    BTW, I am suing this version. And the vbit in this version does not have "rise delay"/"fall delay". 

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