How to measure the performance of a PLL ?

Hi, 

I recently built up a CMOS PLL circuit .  And so far, in the trans simulation, it would be stable (locked to reference frequency) after a few uS.

My questions are :

1. What kind of simulations would be applied to measure the performance of PLL in general? Because we can only run the trans simulation right now.

2. I tried to run pss, however, as we have another signal source as reference signal, pss simulation would not tolerate that. Is PSS possible and necessary?

3. I tried to run HB simulation, the data it generated is soooooo much which filled our disk and errors showed up. So I guess that is impossible for me .

4.I saw many papers ploting the closed loop gain and phase margin. But I don't know what simulation gives that result ? What should I do if I want to see the closed loop gain and phase margin ? What's the meaning of that two figues?

5.The simulation for the whole circuit usually takes few hours with aps++ . Will it be faster if I use spectre X ? It is said it would be faster 3-10 times in the Ad.

If anyone has any suggestion or experience and would like to share with me, I would be grateful.

Thank you !