CDF Parameters: No master specified for instance when running simulation

I've created a simple NOR gate. I want to be able to adjust the width and scaling factor of the NMOS and PMOS transistors in the circuit. Therefore, I have gone ahead and given them the following pPar parameters:

1. pPar("p_m") for the scale factor of the PMOS
2. pPar("p_w") for the width of the PMOS
3. pPar("n_m") for the scale factor of the NMOS
4. pPar("n_w") for the width of the NMOS

An example of how I set it up is shown here:

I then gave these parameters some default values via the Tools -> CDF menu. They look like the following:

All is well. I setup a circuit and then a simulation

However, when I attempt to run this simulation, I am bombarded with a list of errors:

Also, I see new design variables are added to my analog environment window:

I am not sure why I am encountering these issues. I setup the environment variables using pPar so that they can be set from a parent. I also had supplied defaults. How can I resolve this issue?

EDIT: CDS netlisting mode is set to analog (by the way)