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Some DRC errors regarding SP and DP

annieglez92

Hi, I am new using CADENCE, I want to create a layout with DP inside a p Silicon substrate were all my IC will behold. After I run the DRC with Assura I got the following error:

-> (SP, DP) only allowed inside ((RXHV RXHV_IBM) sized by +0.2) sized by -0.2)or in RXHV_IBM touching (text on level RXHV_IBM {NFET12MH_REV_1.0}

I try to fix this creating an RXHV over DP, but then I got this new error which I don't know how o fix:

-> RXHV with 0 or more than 1 RXHV label cadence 

Can anyone help me with this problem? Thanks

  • Andrew Beckett

    These errors are specific to the technology you're using. So I'd suggest mentioning which process technology you're using in the hope that somebody will be familiar with that technology (i.e. foundry, which I assume is IBM/GF from the names you mention), but also the specific technology name.

    You may be better off contacting the foundry (if this is not clear from the design rule manual). It may be hard for people to answer here without violating NDA.

    Regards,

    Andrew.

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