Is it possible to pour a plane in Virtuoso?

I have a design that comprises an array of cells that each contain an isolated stack of VDD! and VSS! vias. The cells are made such that they already do correctly hook themselves up to VDD! and VSS! busses at the top met-6 level, although no such supply bussing exist below met-6 (if you don't include the substrate and well contacts at the bottom of the stacks). Any transistors needing supply connections have routes making their way to any one of those via stacks.

I'd like to do the equivalent of a feature routinely found in PCB layout software i.e. pouring a plane, whereby I draw e.g. a VDD! a rectangle around (or even within) the array on a particular layer and it automatically connects to all VDD! nets within the rectangle but carves out the appropriate clearances to everything else. I want to do this to both reduce the parasitic supply resistance and to also shield many of the sensitive nodes at the lower levels from each other. Is this possible in Virtuoso?