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Wrong Constraint Values in Sequential Cell Characterization

anurans
anurans over 5 years ago

Hi,

I am trying to characterize a D flip-flop for low voltage operation (0.6V) using Cadence Liberate (V16). This is a positive edge triggered D flip flop based on true-single-phase clocking scheme. After the characterization, the measurements reported for hold constraint arcs seem to deviate significantly from its (spectre) spice simulation.

The constraint and the power settings to the liberate are as follows : 

# -------------------------------------------- Timing Constraints --------------------------------------------------------------------------------
### Input waveform ###
set_var predriver_waveform 2;# 2=use pre-driver waveform
### Capacitance ###
set_var min_capacitance_for_outputs 1;# write min_capacitance attribute for output pins
### Timing ###
set_var force_condition 4
### Constraint ###
set_var constraint_info 2
#set_var constraint_search_time_abstol 1e-12 ;# 1ps resolution for bisection search
set_var nochange_mode 1 ;# enable nochange_* constraint characterization
### min_pulse_width ###
set_var conditional_mpw 0
set_var constraint_combinational 2


#---------------------------------------------- CCS Settings ----------------------------------------------------------------------------------------
set_var ccsn_include_passgate_attr 1
set_var ccsn_model_related_node_attr 1
set_var write_library_is_unbuffered 1

set_var ccsp_min_pts 15 ;# CCSP accuracy
set_var ccsp_rel_tol 0.01 ;# CCSP accuracy
set_var ccsp_table_reduction 0 ;# CCSP accuracy
set_var ccsp_tail_tol 0.02 ;# CCSP accuracy
set_var ccsp_related_pin_mode 2 ;# use 3 for multiple input switching scnarios and Voltus only libraries


#----------------------------------------------- Power ---------------------------------------------------------------------------------------------------
### Leakage ###
set_var max_leakage_vector [expr 2**10]
set_var leakage_float_internal_supply 0 ;# get worst case leakage for power switch cells when off
set_var reset_negative_leakage_power 1 ;# convert negative leakage current to 0

### Power ###
set_var voltage_map 1 ;# create pg_pin groups, related_power_pin / related_ground_pin
set_var pin_based_power 0 ;# 0=based on VDD only; 1=power based on VDD and VSS (default);
set_var power_combinational_include_output 0 ;# do not include output pins in when conditions for combinational cells

set_var force_default_group 1
set_default_group -criteria {power avg} ;# use average for default power group

#set_var power_subtract_leakage 4 ;# use 4 for cells with exhaustive leakage states.
set_var subtract_hidden_power 2 ;# 1=subtract hidden power for all cells
set_var subtract_hidden_power_use_default 3 ;# 3=subtract hidden power from matched when condition then default group
set_var power_multi_output_binning_mode 1 ;# binning for multi-output cell considered for both timing and power arcs
set_var power_minimize_switching 1
set_var max_hidden_vector [expr 2**10]
#--------------------------------------------------------------------------------------------------------------------------------------------------------------

I specifically used set_var constraint_combinational 2 in the settings, in case the Bisection pass/fail mode fails to capture the constraints. In my spice simulation, the hold_rise (D=1, CLK=R, Q=R) arc at-least requires ~250 ps for minimum CLK/D slew combination (for the  by default smallest capacitive load as per Liberate)  while Liberate reports only ~30 ps. The define_cell template to this flip flop is pretty generic, which does not have any user specified arcs. So which settings most likely affecting the constraint measurements in Liberate and how can I debug this issue ?

Thanks

Anuradha

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  • Guangjun Cao
    Guangjun Cao over 5 years ago

    Hi Anuradha,

    PLEASE USE LATEST LIBERATE RELEASE, WHEN YOU HAVE AN ISSUE.

    My questions/suggestions are,

    1. use select_index {1} before loading the template

    2. save the pass deck

    3. re-run the decks for the constraint that you have problem with.

    3a. Assuming you do not see a FAIL for the first 3-5 iteration. Normally, the last 5-10 iterations are for final constraint searching. 

    3b. in your logfile, just before the simulation starts, you should see what criteria the tool chooses to use for the arc. For pass/fail look for the point where the output no longer has a full transition or the glitch reaches the threshold you have set(or default). for degradation, find out where the delay is pushed out by the threshold (defined by constraint_delay_degrade).

    Guangjun

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  • anurans
    anurans over 5 years ago in reply to Guangjun Cao

    Hi Guangjun,

    Thanks for your input. So this is what I did to debug the issue : 

    1. Added following debug commands to the script, so that the pass/fail arc instances with the measurement criteria can be clearly observed: 

    select_index -style 1x1 ;# run only 1st point in table

    set_var bisection_info 4 ;# print additional bisection search info to output log
    set_var power_info 2 ;# print additional power calculation info of table's 1st point to file decks/po

    set_var ski_enable 0
    set_var extsim_save_passed all ;# save all run decks and output files
    set_var extsim_save_failed all ;# save all run decks and output files
    set_var extsim_save_verify 2 ;# save verify deck
    set_var extsim_deck_dir [file normalize "decks"] ;# specify directory for SPICE decks and output files
    set_var extsim_tar_cmd "" ;# disable tgz of simulation decks and run logs

    2. The log file says, Liberate uses the default "degradation" criteria for the constraint measurements. By default this must be 10% (?)

    It seemed that the automatic bisection search bound was too large to determine the optimal setup/hold times, so I modified following : 

    set_var constraint_search_bound 3e-10
    set_var constraint_search_bound_estimation_mode 3

    This somewhat improves the accuracy, but I still have few problems :

    1) Even with the above settings, the bisection search step size is still seen to be larger. How can I reduce the step size ? Although there is a variable called constraint_combinational_step_size, this does not seem to have any effect on the actual step size between two iterations !  And how can I add few more iterations assuming the degradation criteria is not violated ?

    INFO (LIB-405): Search setup_5/setup_5_001(TSPC18): type=setup_rising, when=, entry=0, iteration=1, cslew(D-R)=2.5e-12, rslew(CP-R)=2.5e-12, align(D-R->CP-R)=-3.0125e-10, delay(CP-R->Q-R)=1.21979e-09, criteria: degradation, passed
    INFO (LIB-405): Search setup_5(TSPC18): type=setup_rising, when=, entry=0, iteration=2, cslew(D-R)=2.5e-12, rslew(CP-R)=2.5e-12, align(D-R->CP-R)=3.0125e-10, delay(CP-R->Q-R)=-1, criteria: degradation, assumed failed
    INFO (LIB-405): Search setup_5/setup_5_001_iter002(TSPC18): type=setup_rising, when=, entry=0, iteration=3, cslew(D-R)=2.5e-12, rslew(CP-R)=2.5e-12, align(D-R->CP-R)=0, delay(CP-R->Q-R)=-1, criteria: degradation, failed
    INFO (LIB-405): Search setup_5/setup_5_001_iter003(TSPC18): type=setup_rising, when=, entry=0, iteration=4, cslew(D-R)=2.5e-12, rslew(CP-R)=2.5e-12, align(D-R->CP-R)=-1.50625e-10, delay(CP-R->Q-R)=-1, criteria: degradation, failed
    INFO (LIB-405): Search setup_5/setup_5_001_iter003(TSPC18): type=setup_rising, when=, entry=0, iteration=4, cslew(D-R)=2.5e-12, rslew(CP-R)=2.5e-12, align(D-R->CP-R)=-1.50625e-10, delay(MNM11_d)=0.239033, criteria: settled, failed
    INFO (LIB-405): Search setup_5/setup_5_001_iter004(TSPC18): type=setup_rising, when=, entry=0, iteration=5, cslew(D-R)=2.5e-12, rslew(CP-R)=2.5e-12, align(D-R->CP-R)=-2.25938e-10, delay(CP-R->Q-R)=1.30979e-09, criteria: degradation, passed
    INFO (LIB-405): Search setup_5/setup_5_001_iter005(TSPC18): type=setup_rising, when=, entry=0, iteration=6, cslew(D-R)=2.5e-12, rslew(CP-R)=2.5e-12, align(D-R->CP-R)=-1.88281e-10, delay(CP-R->Q-R)=1.43892e-09, criteria: degradation, failed
    INFO (LIB-405): Search setup_5/setup_5_001_iter006(TSPC18): type=setup_rising, when=, entry=0, iteration=7, cslew(D-R)=2.5e-12, rslew(CP-R)=2.5e-12, align(D-R->CP-R)=-2.1661e-10, delay(CP-R->Q-R)=1.33195e-09, criteria: degradation, passed
    INFO (LIB-405): Search setup_5/setup_5_001_iter007(TSPC18): type=setup_rising, when=, entry=0, iteration=8, cslew(D-R)=2.5e-12, rslew(CP-R)=2.5e-12, align(D-R->CP-R)=-2.02446e-10, delay(CP-R->Q-R)=1.37599e-09, criteria: degradation, failed
    INFO (LIB-405): Search setup_5/setup_5_001_iter008(TSPC18): type=setup_rising, when=, entry=0, iteration=9, cslew(D-R)=2.5e-12, rslew(CP-R)=2.5e-12, align(D-R->CP-R)=-2.09528e-10, delay(CP-R->Q-R)=1.35207e-09, criteria: degradation, failed
    INFO (LIB-405): Search setup_5/setup_5_001_iter009(TSPC18): type=setup_rising, when=, entry=0, iteration=10, cslew(D-R)=2.5e-12, rslew(CP-R)=2.5e-12, align(D-R->CP-R)=-2.13069e-10, delay(CP-R->Q-R)=1.34162e-09, criteria: degradation, passed

    2) When we say 10% of delay degradation for "setup", does it mean that the maximum allowable delay on the clk->Q arc is 10% increase of the minimum clk-Q delay (reference) ?

    3) How does Liberate measure this reference value ?

    Anuradha 

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  • anurans
    anurans over 5 years ago in reply to Guangjun Cao

    Hi Guangjun,

    Thanks for your input. So this is what I did to debug the issue : 

    1. Added following debug commands to the script, so that the pass/fail arc instances with the measurement criteria can be clearly observed: 

    select_index -style 1x1 ;# run only 1st point in table

    set_var bisection_info 4 ;# print additional bisection search info to output log
    set_var power_info 2 ;# print additional power calculation info of table's 1st point to file decks/po

    set_var ski_enable 0
    set_var extsim_save_passed all ;# save all run decks and output files
    set_var extsim_save_failed all ;# save all run decks and output files
    set_var extsim_save_verify 2 ;# save verify deck
    set_var extsim_deck_dir [file normalize "decks"] ;# specify directory for SPICE decks and output files
    set_var extsim_tar_cmd "" ;# disable tgz of simulation decks and run logs

    2. The log file says, Liberate uses the default "degradation" criteria for the constraint measurements. By default this must be 10% (?)

    It seemed that the automatic bisection search bound was too large to determine the optimal setup/hold times, so I modified following : 

    set_var constraint_search_bound 3e-10
    set_var constraint_search_bound_estimation_mode 3

    This somewhat improves the accuracy, but I still have few problems :

    1) Even with the above settings, the bisection search step size is still seen to be larger. How can I reduce the step size ? Although there is a variable called constraint_combinational_step_size, this does not seem to have any effect on the actual step size between two iterations !  And how can I add few more iterations assuming the degradation criteria is not violated ?

    INFO (LIB-405): Search setup_5/setup_5_001(TSPC18): type=setup_rising, when=, entry=0, iteration=1, cslew(D-R)=2.5e-12, rslew(CP-R)=2.5e-12, align(D-R->CP-R)=-3.0125e-10, delay(CP-R->Q-R)=1.21979e-09, criteria: degradation, passed
    INFO (LIB-405): Search setup_5(TSPC18): type=setup_rising, when=, entry=0, iteration=2, cslew(D-R)=2.5e-12, rslew(CP-R)=2.5e-12, align(D-R->CP-R)=3.0125e-10, delay(CP-R->Q-R)=-1, criteria: degradation, assumed failed
    INFO (LIB-405): Search setup_5/setup_5_001_iter002(TSPC18): type=setup_rising, when=, entry=0, iteration=3, cslew(D-R)=2.5e-12, rslew(CP-R)=2.5e-12, align(D-R->CP-R)=0, delay(CP-R->Q-R)=-1, criteria: degradation, failed
    INFO (LIB-405): Search setup_5/setup_5_001_iter003(TSPC18): type=setup_rising, when=, entry=0, iteration=4, cslew(D-R)=2.5e-12, rslew(CP-R)=2.5e-12, align(D-R->CP-R)=-1.50625e-10, delay(CP-R->Q-R)=-1, criteria: degradation, failed
    INFO (LIB-405): Search setup_5/setup_5_001_iter003(TSPC18): type=setup_rising, when=, entry=0, iteration=4, cslew(D-R)=2.5e-12, rslew(CP-R)=2.5e-12, align(D-R->CP-R)=-1.50625e-10, delay(MNM11_d)=0.239033, criteria: settled, failed
    INFO (LIB-405): Search setup_5/setup_5_001_iter004(TSPC18): type=setup_rising, when=, entry=0, iteration=5, cslew(D-R)=2.5e-12, rslew(CP-R)=2.5e-12, align(D-R->CP-R)=-2.25938e-10, delay(CP-R->Q-R)=1.30979e-09, criteria: degradation, passed
    INFO (LIB-405): Search setup_5/setup_5_001_iter005(TSPC18): type=setup_rising, when=, entry=0, iteration=6, cslew(D-R)=2.5e-12, rslew(CP-R)=2.5e-12, align(D-R->CP-R)=-1.88281e-10, delay(CP-R->Q-R)=1.43892e-09, criteria: degradation, failed
    INFO (LIB-405): Search setup_5/setup_5_001_iter006(TSPC18): type=setup_rising, when=, entry=0, iteration=7, cslew(D-R)=2.5e-12, rslew(CP-R)=2.5e-12, align(D-R->CP-R)=-2.1661e-10, delay(CP-R->Q-R)=1.33195e-09, criteria: degradation, passed
    INFO (LIB-405): Search setup_5/setup_5_001_iter007(TSPC18): type=setup_rising, when=, entry=0, iteration=8, cslew(D-R)=2.5e-12, rslew(CP-R)=2.5e-12, align(D-R->CP-R)=-2.02446e-10, delay(CP-R->Q-R)=1.37599e-09, criteria: degradation, failed
    INFO (LIB-405): Search setup_5/setup_5_001_iter008(TSPC18): type=setup_rising, when=, entry=0, iteration=9, cslew(D-R)=2.5e-12, rslew(CP-R)=2.5e-12, align(D-R->CP-R)=-2.09528e-10, delay(CP-R->Q-R)=1.35207e-09, criteria: degradation, failed
    INFO (LIB-405): Search setup_5/setup_5_001_iter009(TSPC18): type=setup_rising, when=, entry=0, iteration=10, cslew(D-R)=2.5e-12, rslew(CP-R)=2.5e-12, align(D-R->CP-R)=-2.13069e-10, delay(CP-R->Q-R)=1.34162e-09, criteria: degradation, passed

    2) When we say 10% of delay degradation for "setup", does it mean that the maximum allowable delay on the clk->Q arc is 10% increase of the minimum clk-Q delay (reference) ?

    3) How does Liberate measure this reference value ?

    Anuradha 

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  • Guangjun Cao
    Guangjun Cao over 5 years ago in reply to anurans

    Have you checked the waveforms ? This is the must-do, unless you fins an obvious issue and solution. The logfile information can be used as a guide, in terms of which waveforms to start with or to look into.

    constraint_delay_degrade=0.1 by default. The delay does not change if the two signals are set up well before the constraint. you should find this very obviously through the waveform. constraint_delay_degrade_abstol(default 1ps, minimum supported 0.1ps) is another variable that sets the delay/degradation criteria. 

    if constraint_combinational=0, then the min step may be controlled by constraint_search_time_abstol.

    I would not recommend change the default constraint_search_bound_estimation_mode and even other settings for constraint, unless you checked have checked the waveform and know what parameter to change.

    guangjun

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  • anurans
    anurans over 5 years ago in reply to Guangjun Cao

    Hi Guang,

    Guangjun Cao said:
    The delay does not change if the two signals are set up well before the constraint

    This is obvious. So according to your answer what Liberate seems to be doing is, first, two signals are setup well in advance and measure the minimum clk-Q delay and based on that calculate the point where this delay degrades by 10%.

    Guangjun Cao said:
    Have you checked the waveforms ?

    Yes, I have. I don't see any problem in the waveforms for given iterations. The thing is when I set the set_var constraint_search_bound 3e-10, the search algorithm works better and arrives to more accurate measurement than automatically determined bounds.

    So my last doubt : 

    When both constraint_delay_degrade=0.1 and constraint_delay_degrade_abstol = 1ps (by default) are set, what is the criteria for delay degradation measurement ? Because I do not see the 10% degradation point is met  in the iterations (or in waveforms). i.e. The last "pass iteration" shown for the setup time in the log does not correspond to the 10% degradation point (initial constant clk-Q delay=65 ns, 10% degradation point should be 71.5 ns) . Kindly clarify.....

    Thanks

    Anuradha

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  • Guangjun Cao
    Guangjun Cao over 5 years ago in reply to anurans

    Yes, the tool will find the normal delay, at the boundary that gives the largest setup time. then, the tool will simulate at the opposite boundary, which is supposed to give a more than 10% delay degradation. after this, the tool will reduce the setup time between the signal to find the nearest (no bigger that 2ps tolerance) point where 10% delay degradation is found. with 65ns normal delay, delay degradation by 10%, which means a delay of 71.5, at which the setup is measured.

    Guangjun

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  • anurans
    anurans over 5 years ago in reply to Guangjun Cao

    Thanks. The definition of the criteria is clear to me now although it's bit foggy in the manual. You can consider this as "closed" now.

    Anuradha

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