• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. Verilog-A block works with transient analysis but has no...

Stats

  • Locked Locked
  • Replies 9
  • Subscribers 125
  • Views 20444
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Verilog-A block works with transient analysis but has no output with harmonic balance

MatthewLove
MatthewLove over 5 years ago

I have a sinusoidal voltage source written in Verilog-A (taken from this wikipedia page). I've pasted my slightly-altered code below.

The component generates the correct sine wave output in a transient analysis but there is no output in a harmonic balance simulation. To be precise, the transient output from the HB sim is just noise with a peak amplitude of roughly 1e-33 V.

Does anyone know how to get the model to work for both time-domain and frequency-domain analyses? Do I need to use a conditional based on the analysis and have two different model implementations? I assume the issue lies in the use of $abstime but I haven't found an alternative in the documentation so far.

`include "constants.vams"
`include "disciplines.vams"

module sin_vsource_1(p, n);
    parameter real amplitude = 1.0;
    parameter real f0 = 1G;
    inout p,n;
    electrical p,n;
    analog begin
        V(p, n) <+ amplitude * sin(`M_TWO_PI * f0 * $abstime);
        $bound_step(0.01/f0);
    end
endmodule

  • Cancel
Parents
  • ShawnLogan
    ShawnLogan over 5 years ago

    Dear MathewLove,

    After looking at your code, I am wondering why you are using a veriloga source as opposed to a sinusoidal source from the analogLib library? Unless I am overlooking something in your code, it does not appear that you need to customize the source any more than the customization options provided by the analogLib source.

    I think the use of an analogLib source will eliminate the issue you are observing in an HB analysis unless your analysis or test bench has multiple periodic sources and you are simulating an autonomous oscillator.

    Shawn

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • ShawnLogan
    ShawnLogan over 5 years ago

    Dear MathewLove,

    After looking at your code, I am wondering why you are using a veriloga source as opposed to a sinusoidal source from the analogLib library? Unless I am overlooking something in your code, it does not appear that you need to customize the source any more than the customization options provided by the analogLib source.

    I think the use of an analogLib source will eliminate the issue you are observing in an HB analysis unless your analysis or test bench has multiple periodic sources and you are simulating an autonomous oscillator.

    Shawn

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
  • MatthewLove
    MatthewLove over 5 years ago in reply to ShawnLogan

    I'm just trying to learn the basics of Verilog-A by creating a few simple blocks.

    I don't really care about making a sine-wave generator. I want to find out why the component doesn't work in harmonic balance simulations so I can avoid the issue in future.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • ShawnLogan
    ShawnLogan over 5 years ago in reply to MatthewLove

    Dear MathewLove,

    MatthewLove said:
    I'm just trying to learn the basics of Verilog-A by creating a few simple blocks.

    Thank you - now I understand!

    A couple of thoughts then...

    1. I noticed your code does not contain a specific analysis statement indicating it should be used in a harmonic balance analysis. From version 19.1 of the verilog-a manual:

    at URL:

    https://support.cadence.com/apex/techpubDocViewerPage?path=veriaref/veriaref19.1/veriarefTOC.html

    and shown below as Figure 1, you might try to include the harmonic balance analysis in the list of analyses that your verilog-a block is used. I do not know if the "default" behavior is not to use the function - but that might explain why the output is essentially 0 if the code is simply not used in the harmonic balance analysis. The example they provide shows a means to change the verilog code dependent on the analysis. I might try explicitly including the harmonic balance analysis as one for which your code should be executed.

    if (analysis("dc", "ic"))
    out = ! V(in) > 0.0 ;
    else
    @(cross (V(in),0)) out = ! out
    V(out) <+ transition (out, 5n, 1n, 1n) ;

    So...

    if (analysis("tran" "harmonic"))

    <your_code>

    else

    <assign output to zero or something like that>

    2. As you commented, the use of $abstime may be an issue in a harmonic balance analysis. Once again from the verilog-a manual and shown in Figure 2, depending on the version of MMSIM you are using there may be an error generated from this function in a harmonic balance analysis. You did not mention that spectre reported an error, so perhaps you are using a version of MMSIM greater than 15.1

    Shawn

    Figure 1 (page 149 of v19.1 verilog-a reference manual whose URL is provided above)

    Figure 2 (page 228, 229 of v19.1 verilog-a reference manual whose URL is provided above)

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Andrew Beckett
    Andrew Beckett over 5 years ago in reply to ShawnLogan

    You don't need to have an analysis() check in the code to make this works. There's a special case that you have to do to announce the fundamental frequency in the model so that the RF analyses (well, harmonic balance) know how to deal with the source.

    This is covered in this article: verilogA sin source does not work with hb analysis in spectreRF

    The trick is to use $cds_set_rf_source_info as in this modification of your code (it works properly if you change it to be like this):

    `include "constants.vams"
    `include "disciplines.vams"
    
    module sin_vsource_1(p, n);
        parameter real amplitude = 1.0;
        parameter real f0 = 1G;
        inout p,n;
        electrical p,n;
        parameter string fundname = "rf";
        analog begin
            $cds_set_rf_source_info ( fundname, f0);
            V(p, n) <+ amplitude * sin(`M_TWO_PI * f0 * $abstime);
            $bound_step(0.01/f0);
        end
    endmodule
    Unknown said:
    I think the use of an analogLib source will eliminate the issue you are observing in an HB analysis unless your analysis or test bench has multiple periodic sources and you are simulating an autonomous oscillator.

    I'm also not quite sure why you would need to use a Verilog-A source in the case where you're running semi-autonomous harmonic balance (i.e. with an oscillator as the first tone, and a driven source as the second tone). I don't think that would be necessary.

    Hope that helps!

    Andrew.

    • Cancel
    • Vote Up +1 Vote Down
    • Cancel
  • ShawnLogan
    ShawnLogan over 5 years ago in reply to Andrew Beckett

    Hi Andrew,

    Andrew Beckett said:
    You don't need to have an analysis() check in the code to make this works. There's a special case that you have to do to announce the fundamental frequency in the model so that the RF analyses (well, harmonic balance) know how to deal with the source.

    Thank you for adding your insight! This is not something I have tried, so I too was unaware of the article you referred MatthewLove to. Excellent - thank you! I was also unsure as to whether the analysis list must include the harmonic balance option, and I appreciate your correction. So..."only" ... two demerits for me on this one.

    Shawn

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Andrew Beckett
    Andrew Beckett over 5 years ago in reply to ShawnLogan
    Unknown said:
    So..."only" ... two demerits for me on this one

    Don't worry Shawn - you have plenty of credits for your great responses in this thread: How to convert pnoise to time domain process !

    Andrew

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • MatthewLove
    MatthewLove over 5 years ago in reply to Andrew Beckett

    Thanks for providing that solution Andrew (and Shawn too).

    Regarding Shawn asking if I got any errors, no, it just gave that null output but the simulation completed successfully. I'm using Spectre 17.1.0.270.isr5 64bit (I'm not sure if the MMSIM and Spectre versions are the same but that's all I could find from the log).

    I'll have to get access to the online support again as that reference manual looks a lot newer than the one in my installation (it's a Keysight doc from 2004). It looks useful.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Andrew Beckett
    Andrew Beckett over 5 years ago in reply to MatthewLove

    Matthew,

    Well, you wouldn't have a Keysight manual in a Cadence tools installation (we wouldn't do that), so you should check in the Spectre installation for the documentation there, since it will be present. You can either do:

    `spectre_root`/bin/cdnshelp 

    (those are back quotes, and that's running from the UNIX command line) - and find the VerilogA reference there. Or see where "spectre_root" returns (should be the root of the path that "which spectre" returns - up a level or two) and then look in <SPECTREinstDir>/doc/veriaref/veriaref.pdf - this will be the manual that Shawn showed part of.

    You'll find an example using $cds_set_rf_source_info in this manual too.

    Regards,

    Andrew

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • MatthewLove
    MatthewLove over 5 years ago in reply to Andrew Beckett

    Hi Andrew,

    I checked again and yeah, I found the correct document. I must have misclicked on another file I'd downloaded with a similar name, a galaxy-brain move on my part. Still, problem fixed.

    That back-quote method for finding the path was pretty useful too, thanks.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information