Stats

  • Locked Locked
  • Replies 0
  • Subscribers 125
  • Views 12316
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Bus pin mapping in layout

noramirkh

Dear experts,

When generating or placing pins from schematic to layout, how control mapping of bus pins?

Say how to map sel<0:1> schematic pin to sel[0] and sel[1] layout pins. 

Thanks

Norayr

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.