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  3. How to import schematic of standard cell library into Virtuoso...

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How to import schematic of standard cell library into Virtuoso?

OrangeHalo
OrangeHalo over 5 years ago

Hi all,

I am now importing a TSMC 180nm standard cell library into virtuoso. But I really got missed in the file. As far as I know, I should use gds to import the layout. But how about symbol and schematic, as well as the verlog code?

Now I have .spi file(spice/LVS netlist) and .vlg(verlog code for cells). I think I should get the schematic using spi file. I use File-Import-Spice, but I don`t know what library I should refer to. Could you please give me some information on it? Thanks a lot!

Best,

Haochen

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  • Quek
    Quek over 5 years ago

    Hi Haochen

    You can specify your TSMC 180nm library in "Reference Library List".


    Best regards
    Quek

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  • OrangeHalo
    OrangeHalo over 5 years ago in reply to Quek

    Hi Quek,

    Thank you for your reply. Actually I tried this method, but it failed. As you can see in the log:

    ===================
    Spice In Log File
    ===================
    Parameter file: /tmp/spiceInPg11239
    Import Parameters:
    Netlist file name: /home/hczhang/WorkLib/library/tcb018gbwp7t/unzipped/spice/tcb018gbwp7t_270a/tcb018gbwp7t_270a.spi
    Output library name: tcb018gbwp7t
    Output View Type: schematic
    Schematic view name: schematic
    Netlist view name: netlist_tmp
    Reference Library List: tsmc18 tcb018gbwp7t
    Top cell: top
    Device-mapping not enabled.
    Master Cell for Ground: gnd
    Schematic Generation parameter file: /tmp/schOpts_spiceInPg11239
    Simulator: spectre
    Output Simulator: spectre
    paramCaseValue: default
    Language: SPICE
    Total number of files: 1.

    Netlist File: /home/hczhang/WorkLib/library/tcb018gbwp7t/unzipped/spice/tcb018gbwp7t_270a/tcb018gbwp7t_270a.spi.
    Total number of Subckts: 560.

    ********
    Created tcb018gbwp7t.AN2D0BWP7T:netlist_tmp
    Created net A1.
    Created term A1.
    Created net A2.
    Created term A2.
    Created net Z.
    Created term Z.
    Created net VDD.
    Created term VDD.
    Created net VSS.
    Created term VSS.

    Total number of Insts: 6.

    Inst: M_u3-M_u2
    Found net 'Z'.
    Created net 'net6'.
    Found net 'VSS'.
    Signal VSS set to global.
    Found net 'VSS'.
    Signal VSS set to global.
    Created net 'n'.

    Master Cell: 'n'.
    Did not find 'tsmc18.n:symbol'.
    ERROR (SPICEIN-24): Spice In did not find the symbol view of the master cell 'n' of the instance
    'M_u3-M_u2' in the subcircuit 'AN2D0BWP7T'. Specify the reference library that has the symbol
    view of the master cell, or use device-mapping to map 'n' to a different cell.
    Some device mapping file examples for commonly used components while importing
    a spice netlist include:
    devselect := resistor res
    devselect := capacitor cap
    devselect := inductor ind
    devselect := mutual_inductor mind
    Search 'SPICEIN-24' in Cadence Help for more information.
    INFO (SPICEIN-56): Spice In failed to import the netlist file '/home/hczhang/WorkLib/library/tcb018gbwp7t/unzipped/spice/tcb018gbwp7t_270a/tcb018gbwp7t_270a.spi'. You may like to read the log
    file 'spiceIn.log' for details.

    The tsmc18 library does not include the symbol which is used in the .spi netlist file. I can show you a fragment of the .spi file:

    .subckt AN2D0BWP7T A1 A2 Z VDD VSS
    M_u3-M_u2 Z net6 VSS VSS n w=0.5u l=0.18u
    M_u2-M_u4 X_u2-net6 A2 VSS VSS n w=0.5u l=0.18u
    M_u2-M_u3 net6 A1 X_u2-net6 VSS n w=0.5u l=0.18u
    M_u3-M_u3 Z net6 VDD VDD p w=0.685u l=0.18u
    M_u2-M_u2 net6 A2 VDD VDD p w=0.685u l=0.18u
    M_u2-M_u1 net6 A1 VDD VDD p w=0.685u l=0.18u
    .ends

    Do you have any suggesstion on it?

    Best,

    Haochen

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  • Quek
    Quek over 5 years ago in reply to OrangeHalo

    Hi Haochen

    As stated in the error message, you need to provide device mapping so that spiceIn can map each CDL device to a PDK device.

    ERROR (SPICEIN-24): Spice In did not find the symbol view of the master cell 'n' of the instance
    'M_u3-M_u2' in the subcircuit 'AN2D0BWP7T'. Specify the reference library that has the symbol


    I have the following suggestions:
    a. Have an overview of spiceIn by watching the video in COS article 20418149

    b. If your current stdcell CDL netlist does not has subckt PININFO cmds, use the perl script in COS article 11693840 to get the info from the stdcell verilog netlist. This is important because it allows spiceIn to import the subckts with the correct pin directions. The perl script will also automatically generate a device mapping file. Modify the file and then use it for spiceIn.

    Best regards
    Quek

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  • OrangeHalo
    OrangeHalo over 5 years ago in reply to Quek

    Hi Quek,

    Thank you for your help. I will try that and see if I can solve the problem.

    Best,

    Haochen

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