In a tran sim, first sim subset of schematic then sim whole schematic

Dear sray,

There are a number of parameters that can be changed during a transient analysis as detailed in the link:

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nSoyEAE&pageName=ArticleContent

This list includes a lot more than just the errpreset options.

However, to accomplish what I believe you are describing suggests the netlisting process must be repeated at some time t = t*. I would imagine you might accomplish you objective by using some switches to disconnect the power and inputs/outputs of the subcircuits of interest for t< t*. At t = t*, you woke enable their power and inputs.outputs. Of course, this will keep the same number of nets in your circuit for the entire span of the simulation. However, the impact on simulation time of the subcircuit(s) that are disconnected or powered-down might not be too great as their nodes are quiescent.

Is this methodology something you think might be worth considering?

Shawn

The simple answer is that what was requested originally cannot be done. This would be a major topology change within the simulator, and to be honest I think it's of dubious usefulness. 

You could have two tests in ADE XL/Assembler with different configs, where some of the blocks have "bind to open" set (so they would be omitted) and then you use something from the first test to set up the second test. It's not clear to me what the objective of what is being requested here is, and so that makes it very hard to give advice on how you might go about achieving something like it (given that you can't do exactly what was requested).

Andrew.

Hi Andrew,

I see, thanks for the answer that it cannot be done.

The objective is to speed up the simulation. To be concrete, I am simulating a filter followed by an ADC. The filter has a long time constant. The ADC has a short time constant. The filter takes several ms to reach sinusoidal steady state, only after which the ADC data becomes meaningful. Then, at that time, only a few us of ADC data is needed.

Andrew Beckett said:

You could have two tests in ADE XL/Assembler with different configs, where some of the blocks have "bind to open" set (so they would be omitted) and then you use something from the first test to set up the second test.

Thanks for this suggestion. Perhaps in the first test the ADC can be omitted while the filter can be left to settle, and then the final conditions of the filter from this first test can be used as the initial conditions for the filter in the second test where the ADC would not be omitted.

Thanks,

Subhajit

Hi Andrew,

I see, thanks for the answer that it cannot be done.

The objective is to speed up the simulation. To be concrete, I am simulating a filter followed by an ADC. The filter has a long time constant. The ADC has a short time constant. The filter takes several ms to reach sinusoidal steady state, only after which the ADC data becomes meaningful. Then, at that time, only a few us of ADC data is needed.

Andrew Beckett said:

You could have two tests in ADE XL/Assembler with different configs, where some of the blocks have "bind to open" set (so they would be omitted) and then you use something from the first test to set up the second test.

Thanks for this suggestion. Perhaps in the first test the ADC can be omitted while the filter can be left to settle, and then the final conditions of the filter from this first test can be used as the initial conditions for the filter in the second test where the ADC would not be omitted.

Thanks,

Subhajit

Dear Subhajit,

sray said:

Perhaps in the first test the ADC can be omitted while the filter can be left to settle, and then the final conditions of the filter from this first test can be used as the initial conditions for the filter in the second test where the ADC would not be omitted.

This should work well. I do this all the time when I have what is called a "stiff simulation" where the time constants of a circuit have significantly different ranges (tau_slow >> tau_fast). Specifically, if I have a slow settling AGC loop (tau_slow) that surrounds a high speed amplifier or high frequency oscillator (tau_fast), I will provide a set of initial conditions (derived from a simulation of the AGC over many of its time constants (for example, TSTOP ~ 100* tau_slow)  to the slow settling AGC nodes in a much shorter simulation (TSTOP ~ 100 to 1000 * tau_fast)  where I am most interested in the performance of the high speed amplifier or high frequency oscillator. There is still a transient due to the initial condition of the AGC nodes not being identical to that of the same respective nodes of the combined circuits, but a near steady-state solution occurs much faster than without the initial conditions.

Good luckm Subhajit!

Shawn