staircase function

Since this wasn't a SKILL question, I moved it into the Custom IC Design forum.

Verilog-A is the simplest way. Potentially you could have used an existing Verilog-A model for a DAC, and then maybe an ideal ADC to drive that, but then  you need the right resolution. It's easy enough with Verilog-A.

Here's the code:

// VerilogA for rampgenerator

`include "constants.vams"
`include "disciplines.vams"

//	vramp,  (output) input voltage for comparator, non-inverting
//      clk,  clock signal for the comparator

module rampgenerator(vramp, clk);
input		clk ;
output		vramp ;
electrical 	vramp, clk ;

parameter	vth=1 ;			// clk threshold voltage
parameter	resolution=100u ;	// resolution of the ramp
parameter   maxin = 0.8 ;		// maximum input level
parameter   minin = 0.5 ;
parameter   td = 100p ;	// delay time
parameter	tr = 100p ;	// rise time 
parameter   initdirection = 1;

real    offset ;
integer direction ;

analog
begin
   @(initial_step("static","tran")) begin  // On initialization,
    if (initdirection > 0) begin
	    offset = minin;
        direction = 1 ;
    end
    else begin
	    offset = maxin;
        direction = -1 ;
    end
   end

   @( cross( V(clk)>vth, -1 )) begin
	offset = offset + (direction * resolution) ;
   end 
   
   if(offset > maxin-resolution/2) begin
      direction = -1 ;
   end
   else if(offset < minin+resolution/2) begin
      direction = 1;
   end
   
   V(vramp) <+ transition( offset, td, tr, tr ) ;
	
end
endmodule

You'd need to set minin to 1.1, and maxin to 1.4 on the instance of the symbol (use the "Use tools filter" to see the available parameters on the edit properties for the instance of the ramp generator), set the rise times of the steps appropriately (don't make them too sharp if your ramp is rising slowly) and then use a pulse source to clock the input - that allows you to control the rate of the ramp. Here's a zoomed in picture of the graph it produces:

Andrew