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FreePDK45 usage in Virtuoso

kevin998x

I am using FreePDK45 in Virtuoso, but I faced the following error:

Error found by spectre during circuit read-in.

ERROR (SFE-23): "input.scs" 12: The instance `PM' is referencing an undefined model or subcircuit, `pfet'. Either include the file containing the definition of `pfet', or define `pfet' before running the simulation.

ERROR (SFE-23): "input.scs" 16: The instance `NM' is referencing an undefined model or subcircuit, `nfet'. Either include the file containing the definition of `nfet', or define `nfet' before running the simulation.

Following advices at https://www.edaboard.com/threads/cadence-virtuoso-and-mmsim-installation.305420/page-3 does not really help.

Could anyone advise ?

Parents

  • I downloaded the NCSU FreePDK45 to take a look. You should report this to NCSU because there's a problem with the data they ship.

    In Setup->Model Libraries, you need to add (for example):

    $PDK_DIR/ncsu_basekit/models/hspice/hspice_nom.include

    (there are also files for hspice_ff.include and hspice_ss.include). However there is an error in these files for the 1.4 version of the PDK. In these include files there are lines such as this:

    .inc '$PDK_DIR/ncsu_basekit/models/hspice/tran_models/models_nom/NMOS_VTG.inc
    .inc '$PDK_DIR/ncsu_basekit/models/hspice/tran_models/models_nom/PMOS_VTG.inc

    The quotation marks are not balanced (there's a missing quotation mark at the end of the line) so spectre fails because of the error. You need to fix them all to be like this:

    .inc '$PDK_DIR/ncsu_basekit/models/hspice/tran_models/models_nom/NMOS_VTG.inc'
    .inc '$PDK_DIR/ncsu_basekit/models/hspice/tran_models/models_nom/PMOS_VTG.inc'

    (same for the rest of the lines, in all of the ff and ss files too).

    Having done that, it runs OK in Spectre.

    The documentation for the kit is rather sparse, to say the least. It doesn't even mention how to set it up for HSPICE.

    Perhaps you should consider using gpdk045 instead from http://pdk.cadence.com ?

    Andrew

  • in reply to Andrew Beckett

    Having followed your advice above, spectre is able to load the mentioned model library files.

    However, the same error still persist.  Please see attached the generated schematics netlist as well as full spectre simulation log.


    Fullscreen FreePDK45_error.txt Download 
    Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator
Version 15.1.0.284.isr1 64bit -- 12 Nov 2015
Copyright (C) 1989-2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.

User: hyzhuang   Host: hyspirit   HostID: 7F0100   PID: 5349
Memory  available: 90.7182 MB  physical: 2.7667 GB
Linux   : CentOS Linux release 7.8.2003 (Core)
CPU Type: Intel(R) Core(TM) i7-6700HQ CPU @ 2.60GHz
All processors running at 2592.0 MHz
        Socket: Processors
        0:       0,  1,  2,  3
        
System load averages (1min, 5min, 15min) : 5.2 %, 4.2 %, 2.2 %


Simulating `input.scs' on hyspirit at 6:20:58 PM, Mon Jun 29, 2020 (process id: 5349).
Current working directory: /home/hyzhuang/simulation/tut3cells/spectre/schematic/netlist
Command line:
    /eda/cadence/MMSIM151/tools.lnx86/bin/spectre -64 input.scs  \
        +escchars +log ../psf/spectre.out +inter=mpsc  \
        +mpssession=spectre0_4412_2 -format psfxl -raw ../psf  \
        +lqtimeout 900 -maxw 5 -maxn 5
spectre pid = 5349

Loading /eda/cadence/MMSIM151/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ...
Loading /eda/cadence/MMSIM151/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ...
Loading /eda/cadence/MMSIM151/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ...
Loading /eda/cadence/MMSIM151/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ...
Loading /eda/cadence/MMSIM151/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ...
Reading file:  /home/hyzhuang/simulation/tut3cells/spectre/schematic/netlist/input.scs
Reading file:  /eda/cadence/MMSIM151/tools.lnx86/spectre/etc/configs/spectre.cfg
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/hspice_nom.include
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_nom/NMOS_VTG.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_nom/PMOS_VTG.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_nom/NMOS_VTL.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_nom/PMOS_VTL.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_nom/NMOS_VTH.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_nom/PMOS_VTH.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_nom/NMOS_THKOX.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_nom/PMOS_THKOX.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/hspice_ff.include
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_ff/NMOS_VTG.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_ff/PMOS_VTG.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_ff/NMOS_VTL.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_ff/PMOS_VTL.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_ff/NMOS_VTH.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_ff/PMOS_VTH.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_ff/NMOS_THKOX.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_ff/PMOS_THKOX.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/hspice_ss.include
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_ss/NMOS_VTG.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_ss/PMOS_VTG.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_ss/NMOS_VTL.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_ss/PMOS_VTL.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_ss/NMOS_VTH.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_ss/PMOS_VTH.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_ss/NMOS_THKOX.inc
Reading file:  /media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_ss/PMOS_THKOX.inc
Time for NDB Parsing: CPU = 193.477 ms, elapsed = 255.95 ms.
Time accumulated: CPU = 211.218 ms, elapsed = 255.956 ms.
Peak resident memory used = 44 Mbytes.


The CPU load for active processors is :
        Spectre  0 (39.1 %)      1 (27.3 %)      2 (77.3 %)      3 (68.4 %)
        Other   

Warning from spectre during circuit read-in.
    WARNING (SFE-397): A primitive with name NMOS_VTG already exist, will override.
    WARNING (SFE-397): A primitive with name PMOS_VTG already exist, will override.
    WARNING (SFE-397): A primitive with name NMOS_VTL already exist, will override.
    WARNING (SFE-397): A primitive with name PMOS_VTL already exist, will override.
    WARNING (SFE-397): A primitive with name NMOS_VTH already exist, will override.
        Further occurrences of this warning will be suppressed.
Error found by spectre during circuit read-in.
    ERROR (SFE-23): "input.scs" 15: The instance `PM' is referencing an undefined model or subcircuit, `pfet'. Either include the file containing the definition of `pfet', or define `pfet' before running the simulation.
    ERROR (SFE-23): "input.scs" 19: The instance `NM' is referencing an undefined model or subcircuit, `nfet'. Either include the file containing the definition of `nfet', or define `nfet' before running the simulation.

Reading link:  /eda/cadence/MMSIM151/tools.lnx86/spectre/etc/ahdl/discipline.h
Reading file:  /eda/cadence/MMSIM151/tools.lnx86/spectre/etc/ahdl/disciplines.vams
Reading link:  /eda/cadence/MMSIM151/tools.lnx86/spectre/etc/ahdl/constants.h
Reading file:  /eda/cadence/MMSIM151/tools.lnx86/spectre/etc/ahdl/constants.vams
Time for Elaboration: CPU = 18.483 ms, elapsed = 19.927 ms.
Time accumulated: CPU = 229.923 ms, elapsed = 276.104 ms.
Peak resident memory used = 50.1 Mbytes.


Aggregate audit (6:20:58 PM, Mon Jun 29, 2020):
Time used: CPU = 230 ms, elapsed = 276 ms, util. = 83.3%.
Time spent in licensing: elapsed = 113 ms, percentage of total = 40.7%.
Peak memory used = 50.2 Mbytes.
Simulation started at: 6:20:58 PM, Mon Jun 29, 2020, ended at: 6:20:58 PM, Mon Jun 29, 2020, with elapsed time (wall clock): 276 ms.
spectre completes with 2 errors, 16 warnings, and 0 notices.
spectre terminated prematurely due to fatal error.

    Fullscreen spectre_netlist.txt Download 
    // Generated for: spectre
// Generated on: Jun 29 16:11:30 2020
// Design library name: ADETutorial_2
// Design cell name: tut3cells
// Design view name: schematic
simulator lang=spectre
global 0 vdd!
include "/media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/hspice_nom.include"
include "/media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/hspice_ff.include"
include "/media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/hspice_ss.include"

// Library name: ADETutorial_2
// Cell name: tut3cells
// View name: schematic
PM (out in vdd! vdd!) pfet w=1u l=180.00n as=9.45e-15 ad=9.45e-15 ps=300n \
        pd=300n ld=105n ls=105n m=1
V1 (in 0) vsource type=pulse val0=0 val1=3.3 period=20p rise=1p fall=1p \
        width=9p
NM (out in 0 0) nfet w=2u l=180.00n as=9.45e-15 ad=9.45e-15 ps=300n \
        pd=300n ld=105n ls=105n m=1
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf 
tran tran stop=40p write="spectre.ic" writefinal="spectre.fc" \
    annotate=status maxiters=5 
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
save in out 
saveOptions options save=allpub

  • in reply to kevin998x

    Did you edit the Model Name on the instances of the schematic to be "pfet" and "nfet"? In the PDK I have, they are "PMOS_VTH" and "NMOS_VTH". So you've either edited them or you have an old version of FreePDK45 which has the model names incorrectly specified. If you change them to PMOS_VTH and NMOS_VTH  it should work.

    By the way, you've included the nominal, ff and ss models at the same time. That doesn't make sense, as they all have the same name. This is why spectre complains:

    Warning from spectre during circuit read-in.
    WARNING (SFE-397): A primitive with name NMOS_VTG already exist, will override.
    WARNING (SFE-397): A primitive with name PMOS_VTG already exist, will override.
    WARNING (SFE-397): A primitive with name NMOS_VTL already exist, will override.
    WARNING (SFE-397): A primitive with name PMOS_VTL already exist, will override.
    WARNING (SFE-397): A primitive with name NMOS_VTH already exist, will override.
    Further occurrences of this warning will be suppressed.

    Only include one corner at the same time.

    Andrew.

Reply
  • in reply to kevin998x

    Did you edit the Model Name on the instances of the schematic to be "pfet" and "nfet"? In the PDK I have, they are "PMOS_VTH" and "NMOS_VTH". So you've either edited them or you have an old version of FreePDK45 which has the model names incorrectly specified. If you change them to PMOS_VTH and NMOS_VTH  it should work.

    By the way, you've included the nominal, ff and ss models at the same time. That doesn't make sense, as they all have the same name. This is why spectre complains:

    Warning from spectre during circuit read-in.
    WARNING (SFE-397): A primitive with name NMOS_VTG already exist, will override.
    WARNING (SFE-397): A primitive with name PMOS_VTG already exist, will override.
    WARNING (SFE-397): A primitive with name NMOS_VTL already exist, will override.
    WARNING (SFE-397): A primitive with name PMOS_VTL already exist, will override.
    WARNING (SFE-397): A primitive with name NMOS_VTH already exist, will override.
    Further occurrences of this warning will be suppressed.

    Only include one corner at the same time.

    Andrew.

Children
  • in reply to Andrew Beckett

    Thanks. Your advice above solved the initial FreePDK45 setup in Virtuoso.

    However, the output simulation waveform looked quite strange.
    Please see attached the generated netlist.

    Fullscreen 3146.spectre_netlist.txt Download 
    // Generated for: spectre
// Generated on: Jun 29 18:51:27 2020
// Design library name: ADETutorial_2
// Design cell name: tut3cells
// Design view name: schematic
simulator lang=spectre
global 0 vdd!
include "/media/sf_FreePDK/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/ncsu_basekit/models/hspice/hspice_nom.include"

// Library name: ADETutorial_2
// Cell name: tut3cells
// View name: schematic
NM (out in 0 0) NMOS_VTH w=2u l=180.00n as=9.45e-15 ad=9.45e-15 ps=300n \
        pd=300n ld=105n ls=105n m=1
PM (vdd! in out vdd!) PMOS_VTH w=1u l=180.00n as=9.45e-15 ad=9.45e-15 \
        ps=300n pd=300n ld=105n ls=105n m=1
V1 (in 0) vsource type=pulse val0=0 val1=1.5  period=20p rise=1p fall=1p \
        width=9p
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf 
tran tran stop=40p write="spectre.ic" writefinal="spectre.fc" \
    annotate=status maxiters=5 
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
save in out 
saveOptions options save=allpub




    Simulation waveform without output capacitor:


    Simulation waveform with output capacitor:

  • in reply to kevin998x

    Several things wrong here:

    1. Your netlist does not have the supply source V0 that's in your schematic. So the output waveform you're getting is a result of the devices being supplied through the inout source
    2. The supply (even if it was added) is for 3.3V whereas your pulse has a peak of 1.5V. You'll need to make them consistent
    3. It's a bit optimistic that these devices will operate at 50GHz - the parasitics are too much that. Slow everything down by a factor of 10 to see more realistic waveforms (although there's a nasty overshoot in both directions even with that).
    4. Adding 0.5pF capacitor will dominate - you'd have to operate with a period of 20n rather than 20p for that to be reasonable.

    Anyway, you might want to speak to your supervisor - or whoever came up with the tutorial.

    Andrew.

  • in reply to Andrew Beckett

    Previous Problem solved.

    Below is the CMOS inverter implemented using FreePDK45

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