Stats

  • Locked Locked
  • Replies 7
  • Subscribers 125
  • Views 28018
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

A problem with ports mismatch in LVS

Hamid67

Hi

I am working by xfab 0.35um technology to design an op-amp but I have encountered with a problem. When I want to run LVS through calibre an error is appeared "different numbers of ports". The ports of schematic are recognized but for layout shows zero ports. I should mention that the LVS is ok when I use assura and doesn't show any errors. For simplification I tried to test this issue only by using one nmos and one port but error still exists. The images of the simulation are attached. I would be thankful if anyone could help me.


Regards

Parents
  • wgtkan

    Hamid67,

    I had similar issue like this in the past.  The disadvantage of calibre is that it is case sensitive. 

    This is how  you should fix it: 

    In calibre LVS, go to LVS options  and include tab, under include rule statement, write the following:

    SOURCE CASE YES
    LAYOUT CASE YES

    Thanks

  • Andrew Beckett
    in reply to wgtkan

    I should also point out that asking questions on a Cadence forum about a tool that isn't from Cadence (Calibre is from Mentor) isn't the best place to get answers, although you may luck out and get an answer as you did here.

    Andrew

Reply
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.