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A problem with ports mismatch in LVS

Hamid67

Hi

I am working by xfab 0.35um technology to design an op-amp but I have encountered with a problem. When I want to run LVS through calibre an error is appeared "different numbers of ports". The ports of schematic are recognized but for layout shows zero ports. I should mention that the LVS is ok when I use assura and doesn't show any errors. For simplification I tried to test this issue only by using one nmos and one port but error still exists. The images of the simulation are attached. I would be thankful if anyone could help me.


Regards

Parents
  • wgtkan

    Hamid67,

    I had similar issue like this in the past.  The disadvantage of calibre is that it is case sensitive. 

    This is how  you should fix it: 

    In calibre LVS, go to LVS options  and include tab, under include rule statement, write the following:

    SOURCE CASE YES
    LAYOUT CASE YES

    Thanks

  • Hamid67
    in reply to wgtkan

    Thanks. I did what you said but the hasn't been removed.
    Regards,

  • wgtkan
    in reply to Hamid67

    Hamid67 

    You can’t leave the bulk, drain, and gate terminals floating.
    what error are you getting now?

Reply
  • wgtkan
    in reply to Hamid67

    Hamid67 

    You can’t leave the bulk, drain, and gate terminals floating.
    what error are you getting now?

Children
  • Hamid67
    in reply to wgtkan

    I put pins for other terminals of mosfet. But there is a mismatch in number of ports, ports can't be identified by the layout as the below image.

  • Hamid67
    in reply to Hamid67

    I found the solution. I had to change the label material from MET1  to CETXT. In this case error is removed and LVS is passed.
    Cheers,

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