System Verilog outputs connected in parallel causes voltage division

Dear HoWei,

HoWei said:

But if "real" outputs are connected together, the interface elements (IE) are creating a voltage divider due to their finite output resistance.

The question is, if it is possible to declare a "real" output as high-Z or equivalent ?

And/or what is the better way to model "real-valued" parallel connected outputs ?

It may be my ignorance, and excuse me if it is, but why would you not want to include the impact of their output impedance? It seems your simulation results will not be accurate unless you include the real output impedance.

Shawn

Hi Shawn,

I am open for any suggestion - can you elaborate more on your proposal ?

How can I include the impact of their output impedance ?

The goal is to have a correct output signal for a single cell and for multiple cells connected together.

In Verilog-A I could evaluate the currents and voltages of the output node, but in System Verilog ?

HoWei

I now found some description of using the "EE_pkg" definitions within Cadence.

There are some examples available on how to solve the interface connections in terms of V,I,R.

This seems the way to go forward with SystemVerilog, as its resolution functions are already defined in the Cadence environment.

This is definitely a good solution. You will probably need an Xcelium DMSO license for this, however.

Yes, that is correct - and luckily we do have it.

I already ran the EEnet examples and was able to create my own cells.

The node voltage with multiple outputs is solved correctly.

What I am missing is a tutorial or documentation/presentation on the EEnet package.

Currently I only have the text-files within the cadence environment.

Do you know a good resource / tutorial /documentation of the EEnet package ?

You will find a lot of resources if you search support.cadence.com for EE_pkg or EEnet. One of them is the RAK Using EEnet to perform Electrical Equivalent Modeling in SystemVerilog. You can also take a look at the Mixed Signal Rapid Adoption Kits (RAK) Download Landing page.

Thanks Frank - very helpful !

One (last) question - as it seems you have also used this EEnet within AMS simulations:

From time to time it happens that I cannot extract SV files/modules, which were working without error before ( "package cannot be bound" or other errors). It turned out that I have to search for "*.pak" files within all  involved libraries and delete them manually to be able to compile/extract again - thats really bullsh*t - and it seems that there is no clear structure to overcome this. Well, I have to read the above mentioned documents.

The Cadence Forum and Support Cases were not very helpful …

If you have any trick or suggestion how to avoid this problems, please let me know !

You could try the -cleanlib option of xrun, see https://support.cadence.com/apex/techpubDocViewerPage?path=xrun/xrun20.03/The_XRUN_Command.html#TheXRUNCommand-xrunOptionsCommand-LineOptions. The other -clean... options might be useful as well.

That is doing what I was looking for

BUT when adding the option in a ADE Explorer or Assembler it only is added when starting a simulation, not during compile/extract after a change in the SV file.

I want to add this option during the compile/extract after changing a file. I tried to find a way to add this option via the text-editor GUI - but no success.

How can I add this option to the "xrun" command within the text-editor - any idea ?

Very helpful is to just run "xrun -cleanlib" from inside the workarea where cds.lib is defined.

Do you think this is dangerous ?

You might want to try the approach described at https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V00000911PEUAY for adding the option to the xrun command within the text editor. It's probably not dangerous to recompile everything each time, but it might be rather time-consuming.