Netlist Extraction

I'm assuming by "Netlist Extraction" you're talking about "Parasitic Extraction"? What is commonly done is that after running LVS (Layout Vs Schematic) to ensure the design is laid out correctly, you would then run a parasitic extraction tool (e.g. Quantus QRC, Star RC etc) to extract parasitic resistances and capacitance (and sometimes inductance and mutual inductance) from the interconnect in the layout, and producing a netlist (or netlistable view such as an extracted view or smart view) which contains the design devices, albeit with measured parameters from the layout so can include layout dependent effects like length-of-diffusion, STI, stress parameters, well-proximity effects and so on, as well as replacing the ideal connections between the devices with these parasitic components. 

This is then simulated to check that performance and function of the circuit is still correct; there will be some degradation with respect to your schematic design, and that degradation is more severe at higher frequencies, and typically gets worse as you work in smaller process geometries. That said, don't assume that large-scale process nodes don't suffer from parasitic effects - early in my design career I had a problem in an ADC design in 3um CMOS due to parasitic coupling of tracks (at the time my parasitic extraction tool was a plot of the layout, a ruler, and some hand calculations!)

Regards,

Andrew.