Prevent simulation of specific cell views

Dear Paul,

Is there a reason you cannot create a config view of your test bench and instantiate the extracted view name of your circuit under test in lieu of the schematic view? It seems as this will totally avoid the possibility that your schematic view is used in netlisting. However, I may not fully appreciate your problem.

I can think of a few ways to verify a netlist does not use the schematic view of a given cell, but using a config view appears to eliminate the possibility.

Shawn

Hi Shawn, of course the config view is the default method used. It is just a safety measure, since 'schematic' is part of the standard view list, but the config has to be manually activated. It happend before, that people simulated with the schematic without noticing.

Dear Paul,

Unknown said:

It is just a safety measure,

I now understand your motivation - thank you!

The following article details one method in which you essentially "black box" your device under test with a symbol that contains its inputs and outputs. The netlist you wish to actually use in your simulation is added as an include file. Hence, the netlister does not netlist your design when it is invoked as the black box. This assumes you have a copy of the netlist created from the extracted view of interest.

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nXEGEA2&pageName=ArticleContent

A second method might be to run a script before running a simulation where the script examines the netlist and verifies the cell under test uses an exracted view. Assembler supports the use of a pre-run script using ocean. Ocean can access the UNIX shell - so your script might also be a shell script using sed and awk to examine the netlist. A link to setting up a pre-run ocean script in Assembler is:

https://support.cadence.com/apex/techpubDocViewerPage?xmlName=assembler.xml&title=Virtuoso%20ADE%20Assembler%20User%20Guide%20--%20Running%20Simulations%20-%20Running%20Pre-run%20Scripts%20before%20Simulation%20Runs&hash=pgfId-1059142&c_version=ICADVM18.1&path=assembler/assemblerICADVM18.1/asmSimulating.html#pgfId-1059142

Hope this provides some help anyway...

Shawn

Dear Paul,

Unknown said:

It is just a safety measure,

I now understand your motivation - thank you!

The following article details one method in which you essentially "black box" your device under test with a symbol that contains its inputs and outputs. The netlist you wish to actually use in your simulation is added as an include file. Hence, the netlister does not netlist your design when it is invoked as the black box. This assumes you have a copy of the netlist created from the extracted view of interest.

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nXEGEA2&pageName=ArticleContent

A second method might be to run a script before running a simulation where the script examines the netlist and verifies the cell under test uses an exracted view. Assembler supports the use of a pre-run script using ocean. Ocean can access the UNIX shell - so your script might also be a shell script using sed and awk to examine the netlist. A link to setting up a pre-run ocean script in Assembler is:

https://support.cadence.com/apex/techpubDocViewerPage?xmlName=assembler.xml&title=Virtuoso%20ADE%20Assembler%20User%20Guide%20--%20Running%20Simulations%20-%20Running%20Pre-run%20Scripts%20before%20Simulation%20Runs&hash=pgfId-1059142&c_version=ICADVM18.1&path=assembler/assemblerICADVM18.1/asmSimulating.html#pgfId-1059142

Hope this provides some help anyway...

Shawn

Paul,

A couple of approaches I can think of for this, and I've attached a small example (mylib/lvsblock - with three views, schematic (the LVS schematic), schematicSim (for simulation), and schematicAssert (using a different approach to block simulation)).

The simplest approach is to just place two voltage sources in parallel in your LVS schematic (I had them with different voltages just in case we ever do some optimisation to collapse identical voltage sources in the future). The vdc component in analogLib already has lvsIgnore=true so it will get skipped for CDL netlisting. Spectre will then fail with:

Fatal error found by spectre during topology check.
    FATAL: The following branches form a loop of rigid branches (shorts) when added to the circuit:
        I0.V1:p (from I0.net8 to I0.net7)

Looking at the schematic for I0, the user would see a big label describing why it fails and that this is for LVS purposes.

A second approach can seen in the view schematicAssert. This has an instance of a component called failSim (in the same library) which I just created a symbol with no pins, and then defined CDF to netlist it as a spectre assert statement (note I didn't need to write any custom netlist procedure - you can do this just with appropriate CDF settings, as can be seen in the CDF for failSim). The simulation then fails with:

Fatal error found by spectre at time = 1 ns during transient analysis `tran'.
    FATAL (SPECTRE-4055): I0.I0: This schematic is for LVS purposes only. Expression `1' is true.

This might be a bit more explicit. The downside is that asserts can be turned off (-docl on the spectre command line, and dochecklimit=no on the Simulation->Options->Analog Check tab). The failSim also has lvsIgnore=t on it, plus nlAction=ignore on the auCdl view for good measure (shouldn't be necessary, but just in case!)

Anyway, a couple of choices for you to explore.

Regards,

Andrew.

https://community.cadence.com/cfs-file/__key/communityserver-discussions-components-files/38/lvsSchematic.tgz

Hi Andrew, thank you for the effort. The approach with the assert is exactly what I was looking for. I can even specify the message directly for the simulator output.