LVS not able to read layout with hierarchy.

Faisal,

I'm guessing something is wrong with the CDL netlist. Can you go to the Files tab in the debug environment, and in the Input Files section, find the Schematic Netlist. Please paste the content here (ideally not as a screenshot, as it's much harder to read that way, and this isn't going to be that long).

Andrew.

Hi Andrew,

I sent the netlist for SL_PARINV_test

* +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ *
* CDL Netlist: *
* *
* Cell Name : SL_PARINV_test *
* Netlisted : Tue Aug 25 08:56:34 2020 *
* PVS Version: 19.12-s008 Mon Jan 13 18:07:50 PST 2020 *
* +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ *
*.LDD
*.DEVTMPLT 0 MN(N_18_CIS_MM) RBNGAT NSD(D) PLY(G) NSD(S) PSUB(B)
*.DEVTMPLT 1 MP(P_18_CIS_MM) RBPGAT PSD(D) PLY(G) PSD(S) WEL(B)
*.DEVTMPLT 2 MN(N_33_CIS_MM) TRBNGAT NSD(D) PLY(G) NSD(S) PSUB(B)
*.DEVTMPLT 3 MN(N_33_CIS_MM) TRBNGAT_TW NSD(D) PLY(G) NSD(S) ISOPW(B)
*.DEVTMPLT 4 MP(P_33_CIS_MM) TRBPGAT PSD(D) PLY(G) PSD(S) WEL(B)
*.DEVTMPLT 5 MN(N_LV_33_CIS_MM) TRBNGAT_LV NSD(D) PLY(G) NSD(S) PSUB(B)
*.DEVTMPLT 6 MP(P_LV_33_CIS_MM) TRBPGAT_LV PSD(D) PLY(G) PSD(S) WEL(B)
*.DEVTMPLT 7 MN(N_LV_18_CIS_MM) RBNGAT_LV NSD(D) PLY(G) NSD(S) PSUB(B)
*.DEVTMPLT 8 MP(P_LV_18_CIS_MM) RBPGAT_LV PSD(D) PLY(G) PSD(S) WEL(B)
*.DEVTMPLT 9 MN(N_ZERO_18_CIS_MM) NVTNGAT NSD(D) PLY(G) NSD(S) PSUB(B)
*.DEVTMPLT 10 MN(N_ZERO_33_CIS_MM) TNVTNGAT NSD(D) PLY(G) NSD(S) PSUB(B)
*.DEVTMPLT 11 MP(P_L560_G2) RBPGAT_B6T560 PSD(D) PLY(G) PSD(S) WEL(B)
*.DEVTMPLT 12 MN(N_PG560_G2) RBNPG_B6T560 NSD(D) PLY(G) NSD(S) PSUB(B)
*.DEVTMPLT 13 MN(N_PD560_G2) RBNPD_B6T560 NSD(D) PLY(G) NSD(S) PSUB(B)
*.DEVTMPLT 14 R(RSNWELL) WRES WEL(POS) WEL(NEG)
*.DEVTMPLT 15 R(RSND) SNSRES NSD(POS) NSD(NEG)
*.DEVTMPLT 16 R(RSPD) SPSRES PSD(POS) PSD(NEG)
*.DEVTMPLT 17 R(RSNPO) SNPYR PLY(POS) PLY(NEG)
*.DEVTMPLT 18 R(RSPPO) SPPYR PLY(POS) PLY(NEG)
*.DEVTMPLT 19 R(RNND) NSNSRES NSD(POS) NSD(NEG)
*.DEVTMPLT 20 R(RNPD) NSPSRES PSD(POS) PSD(NEG)
*.DEVTMPLT 21 R(RNHR1000_WG30_CIS_MM) NSHRPYR PLY(POS) PLY(NEG) WEL(SUB)
*.DEVTMPLT 22 R(RNNPO_WG30_CIS_MM) NSNPYR PLY(POS) PLY(NEG) PSUB(SUB)
*.DEVTMPLT 23 R(RNPPO_WG30_CIS_MM) NSPPYR PLY(POS) PLY(NEG) WEL(SUB)
*.DEVTMPLT 24 C(MIMCAPS_CIS_MM) CMMC MMC(POS) SEC_LAST_MET(NEG)
*.DEVTMPLT 25 C(PIPCAPS_CIS_MM) PIPCAP PIP1(POS) PLY(NEG)
*.DEVTMPLT 26 D(DIOP_CIS_MM) DPDIOD PSD(POS) WEL(NEG)
*.DEVTMPLT 27 D(DION_CIS_MM) DNDIOD PSUB(POS) NSD(NEG)
*.DEVTMPLT 28 D(DIONW_CIS_MM) NWNACT PSUB(POS) NSD(NEG)
*.DEVTMPLT 29 Q(PNP_V50X50_CIS_MM) ACTBJT5 PSUB(C) WEL(B) PSD(E)
*.DEVTMPLT 30 Q(PNP_V100X100_CIS_MM) ACTBJT10 PSUB(C) WEL(B) PSD(E)

* +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ *
* Sub cell: pfet_CDNS_4 *
* +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ *
.subckt pfet_CDNS_4 1 2 3
** N=4 EP=3 FDC=1
M0 1 3 2 2 P_18_CIS_MM L=1.8e-07 W=2e-06 $X=0 $Y=220 $dt=1
.ends pfet_CDNS_4

* +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ *
* Sub cell: nfet_CDNS_5 *
* +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ *
.subckt nfet_CDNS_5 1 2 3 4
** N=4 EP=4 FDC=1
M0 1 3 2 4 N_18_CIS_MM L=1.8e-07 W=2e-06 $X=0 $Y=220 $dt=0
.ends nfet_CDNS_5

* +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ *
* Sub cell: SL_PARINV *
* +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ *
.subckt SL_PARINV GND VCC IN OUT 5
** N=5 EP=5 FDC=2
X0 OUT VCC IN pfet_CDNS_4 $T=1500 5800 0 0 $X=580 $Y=5590
X1 OUT GND IN 5 nfet_CDNS_5 $T=1500 1400 0 0 $X=790 $Y=1300
.ends SL_PARINV

* +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ *
* Sub cell: SL_PARINV_test *
* +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ *
.subckt SL_PARINV_test
** N=8 EP=0 FDC=4
X0 1 2 3 4 1 SL_PARINV $T=1000 500 0 0 $X=1580 $Y=460
X1 5 6 7 8 1 SL_PARINV $T=5250 500 0 0 $X=5830 $Y=460
.ends SL_PARINV_test

this is cdl netlis

CDL Netlist:
* Cell Name: SL_PARINV_test
* Netlisted on: Aug 25 08:56:04 2020
*****************************************************************************

*****************************************************************************
* BIPOLAR Declarations
*****************************************************************************
*.BIPOLAR
*.RESI = 2000.000000
*.RESVAL
*.CAPVAL
*.DIOPERI
*.DIOAREA
*.SCALE METER

*****************************************************************************
* Parameter Statement
*****************************************************************************
.PARAM

*******************************************************************************
* Sub-Circuit Netlist: *
* *
* Library: SLIA180_128X8X3CM16 *
* Cell : SL_PARINV *
* View : schematic *
* Last Time Saved: Jul 21 02:03:02 2020 *
*******************************************************************************
.subckt SL_PARINV VCC GND IN OUT
*.PININFO VCC:O GND:I IN:I OUT:I
.ends SL_PARINV

*******************************************************************************
* Main Circuit Netlist: *
* *
* Library: SLIA180_128X8X3CM16 *
* Cell : SL_PARINV_test *
* View : schematic *
* Last Time Saved: Aug 25 07:59:13 2020 *
*******************************************************************************
.subckt SL_PARINV_test A_OUT B_OUT VCC A_IN B_IN GND
*.PININFO A_OUT:O B_OUT:O VCC:O A_IN:I B_IN:I GND:I
XI0 VCC GND A_IN A_OUT SL_PARINV
XI1 VCC GND B_IN B_OUT SL_PARINV
.ends SL_PARINV_test

I not ready good to read this netlis please advice.

Regards

Faisal

Hi Faisal,

The subckt SL_PARINV appears to be empty and is missing transistors. Can you look at the SL_PARINV schematic and check the contents? If you do File->Export->CDL and netlist SL_PARINV_test, does the same thing happen? If there are transistors in SL_PARINV, do they have a property on the instance, e.g. lvsIgnore=t or nlAction=ignore?

I suspect this would be much easier to debug via customer support, to be honest.

Andrew.