Stats

  • Locked Locked
  • Replies 3
  • Subscribers 125
  • Views 12970
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

LVS with backend kit

NickJ

I'm trying to LVS a design made using a backend kit. 

There's main part of the design was created in the analogue flow which lvs's as every cell has schematics.

The top level of the chip has some standard cell logic cells that have no schematic view, and a digital block created in encounter (this has verilog code associated with it)

I've tried to black box the cells in calibre, but I'm afraid my knowledge of how to do that isn't up to snuff.

Can anyone lend me some advice on how to LVS such a design?

Parents
  • Andrew Beckett

    If you're using Calibre to LVS the design, I think it would make far more sense to ask this question to Mentor (either their support or on their forums, assuming they have them still) as Calibre is a Mentor product, not a Cadence product.

    Regards,

    Andrew.

Reply
  • Andrew Beckett

    If you're using Calibre to LVS the design, I think it would make far more sense to ask this question to Mentor (either their support or on their forums, assuming they have them still) as Calibre is a Mentor product, not a Cadence product.

    Regards,

    Andrew.

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.