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Error in running AMS simulation

rezarmzn over 4 years ago

I have a simulation with a systemVerilog module and an analog block and trying to simulate them together.

1. Using ADE XL

2. Have set the simulator to ams

3. Set my connect rules

4. Made config view with AMS template

When I run, I get the error. The following is the irun logfile:

/////////////////////////

irun(64): 15.20-s049: (c) Copyright 1995-2018 Cadence Design Systems, Inc.
TOOL: irun(64) 15.20-s049: Started on Nov 10, 2020 at 11:14:18 PST
irun
-f irunArgs
-clean
-UNBUFFERED
-cdslib ./cds.lib
-noupdate
-errormax 50
-status
-nowarn DLNOHV
-nowarn DLCLAP
-v93
-incdir /ws/ld50/p41/cds/
-ade
-timescale 1ns/1ns
-vtimescale 1ns/1ns
-delay_mode None
-novitalaccl
-access r
-noparamerr
-amspartinfo ../psf/partition.info
-rnm_partinfo
-modelincdir /ws/ld50/p41/cds/
./spiceModels.scs
./amsControlSpectre.scs
-input ./probe.tcl
-run
-exit
-ncsimargs "+amsrawdir ../psf"
-spectre_args "-ahdllibdir /sim/ld50/P41_19SC800_01A_tb/offset_canc_fsm_tb/adexl/results/data/Interactive.4/sharedData/Job3/ahdl/input.ahdlSimDB"
-spectre_args +logstatus
-simcompatible_ams spectre
-name P41_19SC800_01A_tb.offset_canc_fsm_tb:config_ams
-allowredefinition
-amsbind
-top P41_19SC800_01A_tb.offset_canc_fsm_tb:schematic
-top cds_globals
./netlist.vams
./ie_card.scs
-f ./textInputs
-amscompilefile "file:/ws/ld50/p41/cds/P41_19SC800_01A_tb/adc_offset_cal/systemVerilog/verilog.sv lib:P41_19SC800_01A_tb cell:adc_offset_cal view:systemVerilog"
-makelib P41_19SC800_00A
-makelib P41_19SC800_01A
-endlib
./cds_globals.vams
-l ../psf/irun.log
-spectre_args ++aps
-spectre_args +mt=8
irun: *N,CLEAN: Removing existing directory ./INCA_libs.
file: ./netlist.vams
module P41_19SC800_01A.ref_top_v1:schematic
errors: 0, warnings: 0
module P41_19SC800_01A.adc_th_a1_cc:schematic
errors: 0, warnings: 0
module P41_19SC800_01A.adc_async_dynamic_SAR_logic_p41_v1:schematic
errors: 0, warnings: 0
module P41_19SC800_01A.adc_comparator_cap_adjust_pos:schematic
errors: 0, warnings: 0
module P41_19SC800_01A.adc_comparator_a1:schematic
errors: 0, warnings: 0
module P41_19SC800_01A.adc_core_a1_v1:schematic
errors: 0, warnings: 0
module P41_19SC800_01A_tb.offset_canc_fsm_tb:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.ref_buffn:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.ref_buffp:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.ref_core_opamp:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.ref_core:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.adc_core_mom_fill:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.adc_switch2:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.adc_switch3:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.adc_switch1:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.adc_switch_array:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.adc_charge_redistribution_DAC_half:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.adc_charge_redistribution_DAC:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.adc_async_dynamic_SAR_logic_unit1:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.adc_async_dynamic_SAR_logic_delay_cell:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.adc_async_dynamic_SAR_logic_unit2:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.adc_async_dynamic_SAR_logic_sub:schematic
errors: 0, warnings: 0
file: ./cds_globals.vams
module worklib.cds_globals:vams
errors: 0, warnings: 0
file: /ws/ld50/p41/cds/P41_19SC800_01A_tb/adc_offset_cal/systemVerilog/verilog.sv
module P41_19SC800_01A_tb.adc_offset_cal:systemVerilog
errors: 0, warnings: 0
ncvlog: *W,SPDUSD: Include directory /ws/ld50/p41/cds/ given but not used.
Total errors/warnings found outside modules and primitives:
errors: 0, warnings: 1
ncvlog: Memory Usage - 21.3M program + 30.3M data = 51.7M total
ncvlog: CPU Usage - 0.0s system + 0.1s user = 0.1s total (0.1s, 72.7% cpu)
Caching library 'P41_19SC800_01A_tb' ....... Done
Caching library 'worklib' ....... Done
Caching library 'P41_19SC800_01A' ....... Done
Caching library 'P41_19SC800_00A' ....... Done
Elaborating the design hierarchy:
Caching library 'P41_19SC800_00A' ....... Done
Caching library 'P41_19SC800_01A' ....... Done
Caching library 'worklib' ....... Done
Top level design units:
offset_canc_fsm_tb
cds_globals
ncelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
Discipline resolution Pass...
Doing auto-insertion of connection elements...
Connect Rules applied are:
logic_cr
ncelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
Building instance overlay tables: .................... Done
Using implicit TMP libraries; associated with library P41_19SC800_01A_tb
Generating native compiled code:
P41_19SC800_01A_tb.adc_offset_cal:systemVerilog <0x00262eee>
streams: 16, words: 28830
P41_19SC800_01A_tb.offset_canc_fsm_tb:schematic <0x0340a6bf>
streams: 0, words: 0
connectLib.E2L_2:module <0x7d32c189>
streams: 9, words: 9566
connectLib.L2E_2:module <0x20ba3669>
streams: 4, words: 8893
Building instance specific data structures.
Loading native compiled code: .................... Done
Design hierarchy summary:
Instances Unique
Modules: 1386 42
Registers: 109 145
Scalar wires: 30 -
Expanded wires: 3 1
Vectored wires: 17 -
Always blocks: 88 60
Initial blocks: 15 25
Cont. assignments: 20 29
Interconnect: 412 -
Simulation timescale: 1ps
Writing initial simulation snapshot: P41_19SC800_01A_tb.offset_canc_fsm_tb:config_ams
ncelab: Memory Usage - 49.9M program + 59.9M data = 109.8M total (Peak 243.8M)
ncelab: CPU Usage - 0.1s system + 0.2s user = 0.3s total (0.5s, 60.6% cpu)
Loading snapshot P41_19SC800_01A_tb.offset_canc_fsm_tb:config_ams .................... Done
Simulating in AMS-SIE mode...
ncsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
Starting analog simulation engine...
AMSD: Environment variable:
SPECTRE_DEFAULTS = -E
AMSD encountered an error: Invalid command-line arguments for spectre solver: +logstatus
See the Virtuoso AMS Designer Simulator User Guide for valid arguments of spectre solver.
ncsim: *F,RNAERR: The simulator terminated with an analog initialization error.
ncsim: Memory Usage - 38.6M program + 335.3M data = 374.0M total (374.7M Peak)
ncsim: CPU Usage - 0.1s system + 0.0s user = 0.1s total (2.1s, 3.9% cpu)
TOOL: irun(64) 15.20-s049: Exiting on Nov 10, 2020 at 11:14:35 PST (total: 00:00:17)

//////////////////////////////

It worth to mention that the same testbench is just working fine in ADE L.

Regards, Reza

Andrew Beckett over 4 years ago
Hi Reza,

I've reproduced this. You didn't mention which IC version you're using, but as far as I can see it only happens in the latest hot fix of IC6.1.8 or ICADVM20.1 (ISR14), in conjunction with INCISIVE152. It's related to the check for whether +logstatus being added (which is useful for ADE XL/Explorer/Assembler) being based on the capabilities of the spectre that is in the path, not the embedded spectre within the old INCISIVE152 release.

Given that you are using a current IC version (I assume), it seems a bit odd that you're using a 5-year old version of the mixed-signal simulator. If you use XCELIUM20.03 or XCELIUM20.09 (or indeed any XCELIUM version from the tests I did), the problem doesn't occur.

As a workaround (if you really have to use the obsolete INCISIVE152 release), you can enter this (you might need to put this in your .cdsinit if running multiple simulations in ADE):

_amsUISimFeatures->spectre_commandline_logstatus=nil

I filed CCR 2359711 to get this fixed so that it doesn't fail. Hopefully you can confirm that you are indeed using the latest IC6.1.8/ICADVM20.1 hotfix and that you can resolve it ideally by switching simulator versions, or using the SKILL command above (this might have some downsides for spectre simulations - ADE uses this log status to determine whether each analysis was successful so that it can give appropriate messages for expressions - so if tran failed, it doesn't try computing measurements based on tran results because the data may only be from a partial simulation; turning off that log status would prevent that check and so you may appear to get success when something wasn't entirely successful).

Regards,

Andrew.
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rezarmzn over 4 years ago in reply to Andrew Beckett

Hi Andrew,

I don't know how we missed this. Anyway, we just updated to xcelium20.03 and it is working fine now.

Thanks for the help.

Reza
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