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Probing terminals in post-layout simulation

AndreaDY

Hi,

I'm working with a circuit with more than one level of hierarchy like the following:

Each block has a resistor inside:

I made a layout for this that looks like the following (where I marked the terminals of the subcells):

As you can see, part of the routing is inside the subcells and the rest is outside. I made an extracted view of this layout using assura QRC and I created a netlist from this view. I found these parasitic resistors listed in the netlist:

    re2 (\1\:V1 \4\:V1) presistor r=316.615

    re3 (\4\:V1 V1) presistor r=10.4854

    re4 (\4\:V2 V2) presistor r=9.9263

    re5 (\2\:VNEG VNEG) presistor r=9.1725

    re6 (VSUB \1\:VSUB) presistor r=8.7516

    rd10 (\1\:V1 V1) presistor r=10.2233

    rd12 (\4\:V2 \5\:V2) presistor r=330.537

    rd11 (\5\:V2 V2) presistor r=10.1872

    rd7 (\2\:VREF VREF) presistor r=9.4185

I analyzed the netlist by hand and came to the conclusion that the circuit described has the following topology:

Question

My main goal was to probe the sub-blocks' terminals in a post-layout simulation (i.e. I want to know the voltages at the sub-blocks' pins taking into account all the parasitic resistors). I think I wouldn't be able to do this using the existing netlist since:

1) the nodes that correspond to the sub-blocks' pins don't appear in the netlist.

2) the topology is changed, the resistors stars are transformed to triangles.

Then my question is: How should I configure the extraction to preserve the circuit topology?

Additional info

Virtuoso version: IC6.1.8.500.08

Spectre version: SPECTRE 19.1.0.237.isr3

QRC version: EXT 18.2.1-s210

I think the issue may be related to the filtering options I used in the QRC form:

Thank you!

Parents

  • Hi Andrea

    Would doing out-of-context probing be what you need?

    a. Create a config view for your testbench
    b. The DUT in the config view should use the extracted view
    c. Open the testbench from the config view
    d. Run simulation
    e. Descend into the schematic view from the testbench. You should see "out-of-context" in the title bar of the window
    f. Probe the net or terminal


    Best regards
    Quek

  • in reply to Quek

    Hi Quek

    I tried to do out-of-context probing, but I think it is not what I need. What I did was to descend to the first sub-block and probe the pin "A" but when I do this ADEXL loads this output: VDC("/VREF"). This makes sense because VREF and A are the same node in the schematic, but the problem is they are not the same node in the layout. So I wouldn't be able to see the effect of the parasitic resistance this way.

    Thanks

  • in reply to AndreaDY

    Dear AndreaDY,

    For what is worth, the methodology we often follow to examine various input nets in an extractred view based netlist simulation is as follows:

    1. Define a small piece of metal resistor (of the same metal layer as you wish to probe) as a signal probe with a single terminal input terminal and an unconnected output net. You will be saving the unconnected net as a simulation output

    2. Instantiate an instance of the signal probe in your schematic on the net on which you wish to examine.

    3. Save the unconnected end of the signal node as one of your simulation output nodes.

    4. In your layout view, instantiate the small piece of metal (i.e., your defined signal probe) at the specific location in the layout that you wish to plot

    5. Simulation results using either a schematic or extracted view of the resulting subcircuit will now include the net which you wish to examine from the layout.

    Figure 1 shows an example of the signal probe used for one metal layer (metal 1 in this example) in a schematic and Figure 2 shows its schematic.

    Does this help at all?

    Shawn

    Figure 1

    Figure 2

Reply
  • in reply to AndreaDY

    Dear AndreaDY,

    For what is worth, the methodology we often follow to examine various input nets in an extractred view based netlist simulation is as follows:

    1. Define a small piece of metal resistor (of the same metal layer as you wish to probe) as a signal probe with a single terminal input terminal and an unconnected output net. You will be saving the unconnected net as a simulation output

    2. Instantiate an instance of the signal probe in your schematic on the net on which you wish to examine.

    3. Save the unconnected end of the signal node as one of your simulation output nodes.

    4. In your layout view, instantiate the small piece of metal (i.e., your defined signal probe) at the specific location in the layout that you wish to plot

    5. Simulation results using either a schematic or extracted view of the resulting subcircuit will now include the net which you wish to examine from the layout.

    Figure 1 shows an example of the signal probe used for one metal layer (metal 1 in this example) in a schematic and Figure 2 shows its schematic.

    Does this help at all?

    Shawn

    Figure 1

    Figure 2

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