Plot voltage waveform at gate of transistor -RC extraction-.spf file

Dear Hmjafari,

Hmjafari said:

Do you know what is the correct format to include the net in the ADE Assembler output setup? 

Andrew has provided some guidance on the format required to save and access nets in an extracted view based netlist in recent Forum posts that may be helpful. For example:

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/47263/deepprobe-node-name-for-extracted-netlist

Some of his examples are summarized in the Application Note at the On-Line Support URL:

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000003rFo6EAE&pageName=ArticleContent

Nevertheless, I can see that as a minimum, you will need to escape some of the characters. Further, the hierarchy format changes a bit in an extracted view based netlist. The manner in which I often debug the required syntax is to run a VERY short transient simulation (1 to 2 ps? simulation) where I save all the nodes. Using the Results Browser, filter the outputs using for example, a filter "*Mi0:GATE*". This will list the signals that match the gate nodes of MiO. Send that net to the Calculator to view its exact syntax and include it as a file in your simulation with a save statement. As an example of a few save statements within an extracted viewbased netlist, the following is a portion of a file I included in a recent post-layout extracted view based simulation for the gates of some MOS devices:

simulator lang=spectre
save vdda clkin1p clkin1n clk_p clk_n divout_p divout_n \\
vco_divider.mux_0\|mux_p\|cmos_clockmux\|nor2_0\|M1\|GATE \\
vco_divider.mux_0\|mux_n\|cmos_clockmux\|nor2_0\|M1\|GATE \\

...

Note I have escaped the "|" character.

I hope these provide some help!

Shawn

Thanks a lot Shawn, 

When I save all nets and look at results browser, I can plot the net i am looking for. I sent that net to calculator and this is what I have:

v("cdr_vco.vco_biasvosc.osc.oschi.Xbuf0\\/Xinv1p\\<3\\>\\/Xmp1\\/Mi0:GATE" ?result "tran")

I added this net to a save.scs file and loaded that as a model in my corner setup. 

This is how my save.scs file look like:

*********

simulator lang=spectre
save pa_vdda1 \\
cdr_vco.vco_biasvosc.osc.oschi.Xbuf0\\/Xinv1p\\<3\\>\\/Xmp1\\/Mi0:GATE \\

*********

When I try to run the sim, I get this error:

******

Error found by spectre during circuit read-in.
ERROR (SFE-874): "/nfs/site/home/hmazhabj/save.scs" 3: Cannot run the simulation because syntax error `Unexpected hierarchical name "cdr_vco.vco_biasvosc.osc.oschi.Xbuf0\\"' was encountered at line 3, column 0. Correct the syntax error and rerun the simulation.

******

Would you know what's the issue with hierarchical name here?

in my .spf file this is how the net shows:

Xbuf0/Xinv1p<3>/Xmp1/Mi0:GATE

Best,

Hamed

Dear Hamid,

Hmjafari said:

I added this net to a save.scs file and loaded that as a model in my corner setup. 

1. I usually include the added save nets  file as a Simulation file and NOT as a models file. This will put the include statement after the netlist. Did you try this? See Figure 1 and Figure 2 from an Explorer session.

Hmjafari said:

Would you know what's the issue with hierarchical name here?

2. As Andrew noted in his post, the colon is a terminal delimiter in spectre. Hence, you at least need to precede it with an escape character too. If you still get an error, try replacing the colon in your DSPF file to something else that is not a spectre reserved character and use it in your save statement. In the example I provided the ":" indicating GATE are separated by "\|".

Shawn

simulator lang=spectre
save vdda clkin1p clkin1n clk_p clk_n divout_p divout_n \\
vco_divider.mux_0\|mux_p\|cmos_clockmux\|nor2_0\|M1\|GATE \\
vco_divider.mux_0\|mux_n\|cmos_clockmux\|nor2_0\|M1\|GATE \\
vco_divider.mux_0\|mux_p\|cmos_clockmux\|out0b \\
vco_divider.mux_0\|mux_n\|cmos_clockmux\|out0b \\
vco_divider.mux_0\|mux_p\|cmos_clockmux\|nor2_0_out \\
vco_divider.mux_0\|mux_n\|cmos_clockmux\|nor2_0_out \\
vco_divider.mux_0\|mux_p\|cmos_clockmux\|nor2_0\|M3\|DRN \\
vco_divider.mux_0\|mux_n\|cmos_clockmux\|nor2_0\|M3\|DRN \\
vco_divider.mux_0\|mux_p\|cmos_clockmux\|inv_3\|M0\|GATE \\
vco_divider.mux_0\|mux_n\|cmos_clockmux\|inv_3\|M0\|GATE \\

Figure 1

Figure 2

Unknown said:

1. I usually include the added save nets  file as a Simulation file and NOT as a models file. This will put the include statement after the netlist. Did you try this? See Figure 1 and Figure 2 from an Explorer session.

Shawn,

I've not read through all the details in this post (bit busy this week), but the order shouldn't matter. Other than analysis statements, spectre doesn't have an order dependency here - you can specify saves before the netlist is defined, so this shouldn't matter...

Andrew.

Hi Andrew and Shawn, 

Thanks a lot for your reply and detailed explanation. 

In my extraction file I replaced all ”/” and ":" with “_”, then I can use a deepprobe in the schematic to see the signals at the gate or drain of transistor. 

This is the net name I had as probeNode: cdr_vco.vco_biasvosc.osc.oschi.Xbuf0_Xinv0p\<0\>_Xmp1_Mi0_GATE

If I use the same format in a save.scs file and load it as you mentioned I still get a hierarchy error as below:

**********

Error found by spectre during circuit read-in.
ERROR (SFE-874): "../netlist/stimuli/save.scs" 3: Cannot run the simulation because syntax error `Unexpected hierarchical name "cdr_vco.vco_biasvosc.osc.oschi.Xbuf0_Xinv0p"' was encountered at line 3, column 0. Correct the syntax error and rerun the simulation.

**********

This is my current save.scs file:

********

simulator lang=spectre
save pa_vdda1
cdr_vco.vco_biasvosc.osc.oschi.Xbuf0_Xinv0p\<0\>_Xmp1_Mi0_GAT \\
*****

Not sure why the same path doesn't work in save file?

Best,

Hamed

Dear Hmjafari,

Hmjafari said:

This is my current save.scs file:

********

simulator lang=spectre
save pa_vdda1
cdr_vco.vco_biasvosc.osc.oschi.Xbuf0_Xinv0p\<0\>_Xmp1_Mi0_GAT \\
*****

Not sure why the same path doesn't work in save file?

It appears you are missing an "E" in the save.scs file. Is this ia typo? In your deep probe, the expression you provided included an E at the end of your net name.

Shawn

Hi Shawn, Yes I just did not past the whole thing here, the statements are exact same between deepprobe and save file.

Best,

Hamed

I'd strongly suggest you contact customer support. Debugging this without being able to see the data is pretty difficult...

Andrew

Hmjafari said:

Error found by spectre during circuit read-in.
ERROR (SFE-874): "../netlist/stimuli/save.scs" 3: Cannot run the simulation because syntax error `Unexpected hierarchical name "cdr_vco.vco_biasvosc.osc.oschi.Xbuf0_Xinv0p"' was encountered at line 3, column 0. Correct the syntax error and rerun the simulation

Inspecting this error suggests that spectre is not including the remainder of your net name as the name:

cdr_vco.vco_biasvosc.osc.oschi.Xbuf0_Xinv0p\<0\>_Xmp1_Mi0_GATE

is being truncated in the spectre error as:

cdr_vco.vco_biasvosc.osc.oschi.Xbuf0_Xinv0p

This suggests that spectre is not interpreting your escape and <0>. Also, your line continuation character uses a double "\". Did you try the following syntax:

save pa_vdda1 cdr_vco.vco_biasvosc.osc.oschi.Xbuf0_Xinv0p\\<0\\>_Xmp1_Mi0_GATE \\

Shawn

Thanks a lot Shawn and Andrew, 

With the syntax you suggested I still get an error, now its this:

***********

Error found by spectre during circuit read-in.
ERROR (SFE-874): "../netlist/stimuli/save.scs" 3: Cannot run the simulation because syntax error `Unexpected hierarchical name "cdr_vco.vco_biasvosc.osc.oschi.Xbuf0_Xinv0p\<0\>_Xmp1_Mi0_GATE"' was encountered at line 3, column 0. Correct the syntax error and rerun the simulation.

******************

Looks like it sees the whole path but still gets an error.

I will contact cadence support as Andrew suggested.

Thanks a lot for your helps and supports here.

Best,

Hamed