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180nm Calibre PEX error，especially Calview setup error

VictorWu

Hello everyone,
I'm using Charter_018BCD PDK. I made a DAC and have performed DRC, LVS successfully. But when I performed PEX whose output is CalView, I ran into some problems. The error show as follows:
"error: Could not find pin mapping for terminal "SUB" of cell (chart018ull_hv30v nmoscap_1p8 ivpcell). It will remain unconnected."
"error: Could not find pin mapping for terminal "SUB" of cell (chart018ull_hv30v pmoscap_1p8 ivpcell). It will remain unconnected."
"error: Could not find pin mapping for terminal "SUB" of cell (chart018ull_hv30v nmoscap_6p0 ivpcell). It will remain unconnected."
"error: Could not find pin mapping for terminal "SUB" of cell (chart018ull_hv30v nmoscap_6p0_dw ivpcell). It will remain unconnected."
"error: Could not find pin mapping for terminal "SUB" of cell (chart018ull_hv30v pmoscap_6p0 ivpcell). It will remain unconnected."
"error: Could not find pin mapping for terminal "SUB" of cell (chart018ull_hv30v pmoscap_6p0_dw ivpcell). It will remain unconnected."

I don't understand what these errors mean, and what should I do to eliminate these errors.In my circut, there is no pin "SUB". I will attach some screenshots of errors and warnings.

Dose anyone kown how to solve these problems?
Thanks!

Parents

  • BTW, the reason this was marked as spam was because it has lots of repeated text in it - that triggers the spam detection.

    I moved it out of moderation because it's not spam, but that said, posting here is not the best place. Calibre is not a Cadence tool. It's from Mentor (now Siemens) and so you would be far better off asking this question to either Siemens support or in a forum on the Mentor/Siemens site (if there is one - I've not checked recently).

    Regards,

    Andrew

Reply

  • BTW, the reason this was marked as spam was because it has lots of repeated text in it - that triggers the spam detection.

    I moved it out of moderation because it's not spam, but that said, posting here is not the best place. Calibre is not a Cadence tool. It's from Mentor (now Siemens) and so you would be far better off asking this question to either Siemens support or in a forum on the Mentor/Siemens site (if there is one - I've not checked recently).

    Regards,

    Andrew

Children
  • in reply to Andrew Beckett

    An interesting thing is that the most likely root cause of this error is something that straddles Cadence and Mentor tools.
    It's called calview.cellmap file, that provides a mapping between instance terminal names in Virtuoso space to Calibre space - e.g. the terminals in Virtuoso may be called PLUS and MINUS, while in Calibre - POS and NEG, or ANODE and CATHODE.
    It's really unfortunate that semiconductor companies have to deal with these consequences of the miscommunication between major EDA vendors.
    It would be much better if they can agree on the same notations, for the same technology.


       Maxim

  • in reply to MaximX

    Maxim,

    Whilst there are of course many things that EDA vendors don't get right, this is not one of them. The foundry is responsible for the PDK - whatever naming convention they use for the pins is down to them, and the calview.cellmap also is usually provided by the foundry (yes, in some cases the PDKs/verification rules are developed by an EDA vendor on behalf of the foundry, but it's the foundry that owns the flow). This is not a matter of miscommunication between major EDA vendors...

    Andrew

  • in reply to Andrew Beckett

    Thanks, Andrew.

    Theoretically, you are right.
    It's foundry's responsibility to provide a correct calview.cellmap file.
    But I have seen it so often that this is not done properly, and engineers can hardly find any help with this obscure aspect of the design flow.
    I do not know why foundries cannot use the same device pin names in Calibre and in Virtuoso worlds, but indeed, this seems to be dependent more on a foundry, rather than on the EDA vendors side.

    As often happens, each party does their job right, and its at the boundaries, where different parties have to agree on the formats, problems show up.

    Maxim

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