parasitic extraction question on sub-blocks using top-level RCE

What might be the reason, to use higher-hierarchy level parasitic extraction to simulate lower-level block?
Is it required to take into account accurate parasitics (affected by high hierarchy layout), or unavailability (or difficulty to extract) lower-level block?

Dear MaximM

MaximX said:

What might be the reason, to use higher-hierarchy level parasitic extraction to simulate lower-level block?
Is it required to take into account accurate parasitics (affected by high hierarchy layout), or unavailability (or difficulty to extract) lower-level block?

A few reasons come to mind MaximM...

1. If the lower level block has connections that extend from it which are deemed "critical", then if the higher level block's parasitic routing elements are not included, one cannot establish the signal integrity of those "critical" nets of the lower level block.

2. Secondly, the next level of hierarchy (or higher) may have other traces that cross traces of the lower level block. Hence, the use of the higher level of extraction allows one to assess any potential crosstalk into or out of the subcircuit traces in the lower level block.

3. Thirdly, the higher level extraction may contain power or ground traces that form "power grids" that connect to the lower-level block. Hence, without the higher level extracted view based netlist, the actual power or ground resistances of the lower level block cannot be accurately simulated with only an extracted view of the lower level block. This view will also be required in any type of electromigration audit to assess trace current densities are less than the values required for one's reliability requirement.

Does this help your understanding? Of course, from a simulation time perspective, using the an extracted view based netlist for the lowest possible level of schematic hierarchy is preferred - but there are times when the use of a higher schematic hierarchy based extracted view is necessary.

Shawn

Thank you - yes, this makes a perfect sense to me.
Basically, all three reasons you presented, are related to "interaction" between lower-hierarchy level blocks with each other and with higher hierarchy elements, which makes block-level simulation and verification inaccurate (sometimes - very inaccurate, leading to a complete design failure).

We see this sort of effects (caused by parasitics - you do not see this interaction at the schematic level) all the time, when doing analysis at the top level.
The problem is (especially in advanced nodes, lime 7nm or 5nm) - the size and complexity of the top hierarchy level is so high, that standard tools (SPICE, IR/EM, etc.) take too long to be practical.
So, new approaches and solutions are required - and there are a lot of opportunities for innovation in this area.

MaximX said:

So, new approaches and solutions are required - and there are a lot of opportunities for innovation in this area.

That's precisely why there has been innovation in this area. Spectre X technology involves mechanisms to do advanced parasitic reduction - whilst there are a lot of parasitics in advanced nodes, the network can certainly be reduced considerably without a significant impact on accuracy, plus it has mechanisms for more efficient simulation and better scalability across multiple cores and even distributed to multiple machines with a reduced memory footprint.

I would strongly suggest you contact your account team to look at the applicability of Spectre X to your problems.

Andrew

Thank you, Andrew.
Simulation speed is one important factor.

Another factor is - when electrical results from SPICE simulation look bad - where, which layout shape and parasitic elements are causing this?
I don't think that an RC reduction can help with this, for obvious reason - irrespective of the simulation speed.

You can do that part with sensitivity analysis - you can do some sensitivity analysis on the parasitics (although that will need more simulation to be run in order to capture the impact of variations in the parasitics to variations in the measurements). It's not that straightforward to directly infer the impact of an individual parasitic to the output measurements otherwise.

Andrew

Dear MaximX,

If I may add to Andrew's prior comments regarding spectre X...we have adopted its use recently and have found it does significant reduce simulation times for post-layout based netlist simulations. I, personally, have now done a number of comparisons of the results from a spectre X simulation with a spectre +aps simulation and found the two sets of data correlate well for circuits that require high levels of simulator accuracy.

Hence, I fully concur with Andrew that it is worth considering the use of spectre X in your post-layout based netlist simulation efforts.

With regard to your comments, MaximX, regarding "when simulation results look bad...which layout shape..."

Determining the root cause of trace parasitic based, or coupling based mechanism effects due to layout effects is not really the function of any simulator in my view. Maybe I do not fully understand your comment? One can certainly perform sensitivity analyses as Andrew suggests to better understand which parasitic elements contribute to your observed undesired behavior. However, our approach involves using the actual layout to determine trace parasitics along a specific set of traces (including parasitic elements due to its trace segments, vias, and neighboring elements) using an analysis tool we developed. This provides us with an excellent means of establishing which layout features are responsible for undesired circuit performance.

Shawn

There is a tool called ParagonX by a company called Diakopto (https://diakopto.com/) that claims to be able to perform such an analysis. I have never tried it, however, so I have no idea how well it works in practice. You can find some more details at https://www.linkedin.com/pulse/circuit-simulation-parasitics-do-we-need-more-speed-insight-ershov/ (also written by a guy called Maxim...).

Dear Frank,

Frank Wiedmann said:

There is a tool called ParagonX by a company called Diakopto (https://diakopto.com/) that claims to be able to perform such an analysis. I

Thank you! I was not aware of their ParagonX tool. We have a custom tool that we use for what I believe is a similar function. However, I contacted diakopto to find our some more information - thank you again!

Shawn

Dear Frank,

Frank Wiedmann said:

There is a tool called ParagonX by a company called Diakopto (https://diakopto.com/) that claims to be able to perform such an analysis. I

Thank you! I was not aware of their ParagonX tool. We have a custom tool that we use for what I believe is a similar function. However, I contacted diakopto to find our some more information - thank you again!

Shawn