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  3. Why the pulses are not correctly plotted?

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Why the pulses are not correctly plotted?

Ritayan
Ritayan over 4 years ago

Hi,

I am trying to generate a gate pulse by comparing a sawtooth (vramp) (0 to 1.8 volts) with a constant dc voltage ( vcominv) (0.9 volt). I will use that gate pulse to the gate of my MOSFET for close loop buck-boost converter.

Now, I have used a vcvs and also a comparator for the purpose. But the pulse are not exactly what they should be.

This is the schematic.

Now I have done transient analysis (moderate) upto 20ms and the output pulse across (comp and gnd) or (D and x) should be a square pulse with 50% duty cycle varying from 0 to 1.8v.

Now, the output looks like this:

Red: vramp

Green: vcominv

Blue: V(D-x)

Yellow: comp

My questions are

1.why V(D-x) and comp are different?

2. What is the problem in their falling edge? Because there is no problem in rising edge!

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  • ShawnLogan
    ShawnLogan over 4 years ago

    Dear Ritayan,

    Ritayan said:

    1.why V(D-x) and comp are different?

    2. What is the problem in their falling edge? Because there is no problem in rising edge!

    A few questions if I may...

    1. I am not sure what you are using as your model for the comparator, but it appears it may be from the Cadence ahdl library?

    2. Why is the reference input to the comparator net connected to the reference voltage in lieu of the sawtooth waveform? It seems as if the 900 mV reference should be connected to the reference input and the sawtooth the opposite input.

    3. The slopes of the rising snd falling edges of your sawtooth are dramatically different. I do not know the model for your comparator, but it may use the slopes of the crossing to determine its propagation delay time. If so, one would expect the output corresponding to your slower input sawtooth slope to show a finite slope. The output may change very rapidly for the very fast falling edge of the sawtooth. This will explain the reason your "V(D-x)" signal is different than the signal "comp" as the signal "V(D-x)" is hard limited with a fixed very high DC gain.

    In short, I think you need to indicate what model you are using for the comparator for me to better understand the issue you are sobserving. Maybe it is obvious to others on the forum as to the comparator model. I looked int the Cadnece adhl library and there is a comparator, but tis parameters are different than those you indicate. What is the version of spectre you are using?

    Shawn

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  • Ritayan
    Ritayan over 4 years ago in reply to ShawnLogan

    Hi Shawn,

    1. Yes it is from cadence ahdl library. I have set Vhigh=1.8, Vlow=0 and slope=18G V/s that is 1.8V/100ns.

    2. Is there any fixed rule that reference voltage has to be connected to Vref terminal only? Will there be from if I do the opposite. I dont know this. If yes, please let me know.

    3. For sawtooth the slopes of rising edge and falling edge should be drastically different right? I have used pwl so the rising slope is exactly 1.8V/10us and the falling edge slope is exactly 0.

    Ritayan

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  • ShawnLogan
    ShawnLogan over 4 years ago in reply to Ritayan

    Dear Ritayan,

    Ritayan said:
    2. Is there any fixed rule that reference voltage has to be connected to Vref terminal only? Will there be from if I do the opposite. I dont know this. If yes, please let me know.

    I do not know what version of spectre you are using, but your version of the code appears to be missing an offset parameter. The version I am using (20.1.ISR16) has the following parameters:

    // INSTANCE parameters
    //    sigout_high  = maximum output of the comparator  (val)
    //    sigout_low   = minimum output of the comparator  (val)
    //    sigin_offset = subtracted from 'sigin' before comparason to sigref (val)
    //    comp_slope   = determines the sensitivity of the comparator []

    Does your version of the cell use parameter signin_offset? If so, have you specified it?

     If you inspect the veriloga view of the comparator, the output is defined by the tanh function as follows:

         60       V(sigout) <+ 0.5 * (sigout_high - sigout_low)
         61                         * tanh(comp_slope*(V(sigin, sigref)- sigin_offset))
         62                       + (sigout_high + sigout_low)/2;

    Therefore, it does not appear to be "necessary" to set your 900 mV DC source to the vref terminal. However, from a design perspective, it is confusing to see the vref terminal connected to your changing sawtooth input.

    Ritayan said:
    3. For sawtooth the slopes of rising edge and falling edge should be drastically different right? I have used pwl so the rising slope is exactly 1.8V/10us and the falling edge slope is exactly 0.

    You can see why the output is changing in a different fashion by the expression I copied from the veriloga. With a falling transition close to 0, the output will change drastically as it falls. With a relatively slow sawtooth rise time compared to the fall time, the output follows the tanh function and will show the type of behavior you are observing. The fixed gain provided by your controlled voltage source E4 is not a good model of the transfer function of the comparator with the transition time you assigned to your sawtooth waveform.

    I hope this helps Ritayan.

    Shawn

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