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  3. About DC op point and DC sweep

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About DC op point and DC sweep

ichiro
ichiro over 4 years ago

Hi,

Why did I get difference simulation results between DC operating point (-50C) and DC sweep start point (-50C) ?

And how can I correct the phenomenon ?

Thanks,

Ichiro

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  • Andrew Beckett
    Andrew Beckett over 4 years ago

    No idea without seeing the example that produces this. If the difference is very small, it could just be that they are equivalent within tolerances. If the difference is large, it may be that your circuit has multiple stable operating points - there's no guarantee that you'd definitely get the same answer in that case because convergence will often depend on the starting point.

    Most likely you'll need to go to customer support so that you can share your example and an application engineer can investigate further.

    False convergence is extremely rare with spectre (I can't really remember having seen it), but multiple operating points are surprisingly common and people often overlook them. It can also be due to a modelling error - e.g. a VerilogA model that initialises differently, or some incorrect modelling in some other way. That's why it's hard to determine without seeing the circuit (netlist, models and analysis settings) and the symptoms.

    Andrew

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  • Andrew Beckett
    Andrew Beckett over 4 years ago

    No idea without seeing the example that produces this. If the difference is very small, it could just be that they are equivalent within tolerances. If the difference is large, it may be that your circuit has multiple stable operating points - there's no guarantee that you'd definitely get the same answer in that case because convergence will often depend on the starting point.

    Most likely you'll need to go to customer support so that you can share your example and an application engineer can investigate further.

    False convergence is extremely rare with spectre (I can't really remember having seen it), but multiple operating points are surprisingly common and people often overlook them. It can also be due to a modelling error - e.g. a VerilogA model that initialises differently, or some incorrect modelling in some other way. That's why it's hard to determine without seeing the circuit (netlist, models and analysis settings) and the symptoms.

    Andrew

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