Declaration, Initialization and shifting real type arrays in VerilogAMS

This is (as far as I know) not possible as part of the Verilog-AMS LRM. It is possible with SystemVerilog (albeit your examples have the wrong width - they are 5 bits wide and the top has 4 literal values; the bottom example syntax is slightly wrong even with SystemVerilog):

real arr[3:0]={1,2,3,0};

initial begin
  arr={arr[3:2],1.5,2.0};
  $strobe(arr[3]," ",arr[2]," ",arr[1]," ",arr[0]);
end

Andrew

Thanks Andrew.

well, I will write in SV. However, I would like to use also $table_model(), for reading data from a file and assigning it to the array.

Is there any equivalent of $table_model in SV ?

You can use $table_model in Cadence SystemVerilog simulators (both the old INCISIVE and XCELIUM) by passing -rnm_tech to the irun/xrun command line. See this article.

Andrew

Dear Andrew,

Thanks a lot. But, is it possible to add -rnm_tech option while firing the AMS simulation from ADE instead by the command "unix%  xrun filename.sv -rnm_tech".

Yes. On Simulation->Options->AMS Simulator, on the Main tab, go to the bottom, and then there's the "Additional Arguments" button. On the form that then appears, add an additional xrun argument of -rnm_tech - that should do it.

Andrew