Dac verilog ams output FFT plot issue

Are you making sure that the FFT is sampling at the points at which the DAC output has settled? I don't know what version you're using of the IC tools, but in versions before IC6.1.7 you were limited to a power of two sample points in the dft function - if you specified a different value it would round to a power of two (I forget whether it rounded up, down, or to the nearest). From IC617 onwards, it will honour a non-power-of-two number of samples.

Sometimes you may see advice to use strobe period when using the dft function, but assuming that the DAC output is settled for each DAC sample, and you're sampling at those points, this is unnecessary because there's no time interpolation that would occur.

If that's not it, it would be best if you could provide your code, test bench, and stimulus - not too bad if it's entirely behavioural.

Thanks,

Andrew

Thanks for the reply Andrew ,

the version is IC6.1.7 , I am not sure if moving to IC6.1.8 will help ??

I switched to XPS MS mode with ++APS turned on , with that the output after FFT is like the following :

I am still checking on the code part.

regards

I wouldn't expect XPS to be necessary or to help with performance (it wouldn't help with accuracy). The main benefit of XPS is when you have a large chunk of digital transistors.

I don't think moving to IC6.1.8 is going to make a difference here. Something is probably either wrong with the circuit, or your measurement setup. It's really hard to know what without being able to see more information.

Andrew

Dear sidm,

I absolutely agree with Andrew. I highly suspect your simulation setup or your use of the dft() function is likely the source of your confusion. Please include your simulation set-up details, your time domain result, and your post-processing expression using the dft() function if you need any additional thoughts on your issue.

Shawn

thanks for the reply Andrew,

HERE is the snapshot of the equation being used.

I am seeing how to share the other details like testbench etc.

.

The sampling frequency is 450Mhz and simulation time is 30us

I'm a bit confused - you appear to be doing the DFT on VT("/data_out<13:0>") which appears to be a 14-bit bus. I thought this was a DAC? What does the. VT("/data_out<13:0>") waveform look like when you plot the entire simulation results, and perhaps you can zoom in to show a few transitions between codes so that it's clearer how often it is changing.

Of course, this would be much simpler if we could just see the entire setup to work out what you've done wrong.

Andrew.

Dear sidm,

sidm said:

Hi All,

I have a DAC implemented in  verilog ams.

I am giving a 405Mhz digital hex code based digital input.

1. I assume you meant 450 MHz and not 405 MHz in your initial question?

In any case, the expression you provided for the dft() output indicates the reconstruction frequency is 450 MHz.

2. Your initial argument is clearly a digital bus and not the output of the DAC. Hence, you will not find its dft() to appear sinusoidal if your DAC code data_out<13:0> is a digital bus representing a sampled sine wave. To observe the spectrum of your DAC created sinusoid, the first argument must be the DAC analog output(s) - not its digital code inputs.

3. What is the intended DAC sinusoidal output frequency intended to be?

4. The use of the Hanning window will "warp" the output amplitude of your sinusoid. Are you aware of that? In essence, it will not provide the amplitude that you programmed into the DAC input code.

As Andrew noted, you are causing Andrew and I to "guess" both your setup/simulation/simulation results AND your issue. It would be most helpful if you could at least provide the information we requested.

Shawn

thanks for the reply Andrew, the issue is resolved now.

thanks for the reply Andrew, the issue is resolved now.