Instancing schematics in veriloga (or any other analog HDL)

Hello,

I'd like to try running some parametric sweeps in which different numbers of instances are used and / or different connections are used.    So I was going to try using veriloga (or some other analog friendly HDL) to implement the netlist and then sweep the parameter from the top level testbench.

For example, I'd like to do something like this:

parameter NUM_INSTANCES = 5;
my_cell_name
I1 [ NUM_INSTANCES : 1 ]
(in,out);

Problem comes up with netlisting when I have instance_name set to schematic view in the hierarchy editor.

*ERROR* (AMS-2055): The instance 'I1' of cellview 'my_lib_name/my_cell_name/schematic' cannot be instantiated under the cellview 'my_lib_name/my_top_cell_name/veriloga
because the current cellview is not compatible with the master cellview.

Is it not possible to create a netlist with a schematic view underneath a veriloga view?   I've done this with verilog views before but I've never gotten it to work with veriloga.   I want to run pss sims so I can't use verilog.    Are there other analog HDL's which this would work for?   I'm also looking for the ability to instance modules and wires as arrays inside generate constructs so that I can change the connections and/or number of instances for the generated netlist based on a parameter value.   

FYI:

% virtuoso -W
sub-version ICADVM20.1-64b.500.16
% spectre -W
sub-version 19.1.0.428.isr9

Thank you,

Bill Huff