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Partial LVS check

Senan

Hello,

I am laying out big circuit, although I have divided it in sub blocks to make the layout easier, but still I am interesting to see if there is a method to partially check layout versus schematic. As for example, in one block I have a circuit with 40 transistors, and I would like to see the result of the work done with let say 10 transistors before I continue to complete the others, so if there is an error it will be easier to fix before continuing.

Thank you in advance

Regards

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  • Andrew Beckett

    That's kind of the point (or one of the points) of Virtuoso Layout Suite XL - it checks connectivity as you go, and you can use Check Against Source to check parameters too.

    Sure, it's not a signoff tool, but then again the design is not finished so you're not signing it off.

    You can also (with Virtuoso Layout EXL/EAD) use parasitic extraction and capture layout-dependent effects on a partial layout (e.g. using PVS for device parameter extraction), and simulate using those parasitics and LDE parameters on the pieces that have been laid out, but keep the schematic components for everything else. 

    Andrew.

  • Senan
    in reply to Andrew Beckett

    Thank you very much Andrew,

    That was useful and helpful answer

    Have a nice weekend

    Regsrds

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  • Senan
    in reply to Andrew Beckett

    Thank you very much Andrew,

    That was useful and helpful answer

    Have a nice weekend

    Regsrds

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