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Issues in using a Verilog-A output as input to a Verilog-AMS block

RFStuff

Dear All,

My test-bench has both Verilog-A and Verilog-AMS blocks.

The output of a Verilog-A block is used as input of one veriolg-AMS block.

I simply assigned the input of the Verilog-A block to the output of the AMS block. This I have done as :-->

input wreal data_in_from_verilog_a

output wreal data_out

..................

..................

assign data_out = data_in.

But, when I plot data_out, I see the output is staircase type (in other words it changes at certain discrete time instants).

I am not sure on what basis these discrete time points are decided. I have a clocked signal in side the Verilog-AMS block. But the events on this signal doesn't match with the discrete time points.

Could any body please tell how the AMS block decides the discrete time points for the output ?

Kind Regards,

  • Andrew Beckett

    This will be because an E2R (electrical to real) connectmodule is inserted between the electrical output of the Verilog-A and the real input of your VerilogAMS module. Because the wreal is discrete rather than solved this is done in a sampled way, and is controlled by the vdelta parameter of the (default) E2R connect module. If using that, then the default is to have the deltas in terms of changes of greater than vdelta, which will be set to vsup/64. You can control this via the IE card setup (Setup->Connect Rules/IE Setup), and ideally using the IE-card based choice there - this allows you to set the supplies easily for connect modules; vdelta is in the Advanced Setup/Extended section. There are also some time tolerance parameters - to understand them more, you can look at:

    <XCELIUM_OR_INCISIVE_INST_DIR>/tools/affirma_ams/etc/connect_lib/E2R.vams

    Andrew

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