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illegal connection CAD warning message

Hello,

I have at one stage in my layout design when I suddenly received a warning message from annotation browser of CAS tool that I have illegal connection to VDD as shown in the image attached, errors where pointing to the bulks of the PMOS transistors which I connected to VDD and then these bulkes are started to blinks.

However, the design was passing the DRC, and LVS.

What this warning mean ? is it ok to ignore it?

In the next level of layout hierarchy, the warning message from CAS is disappeared. Why?

Thank you in advance

Regards

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