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Adding wreal input and output bus in verilog-AMS

RFStuff over 4 years ago

Dear All,

I need to add wreal input and output bus to a model code written already in VerilogAMS.

I tried to add wreal input/output port like "output wreal [4:0] data_out". But this gives error during compilation.

Is there anyways I can achieve the above ?

Kind Regards,

Andrew Beckett over 4 years ago

See VerilogAMS wreal vectors and arrays . You can use this instead:

output wreal data_out[4:0];

Whilst I found a few discussions about it, I haven't seen any plans to add support to the "before" approach that is in the Verilog AMS LRM. However, practically the "after" approach works...

Andrew
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RFStuff over 4 years ago in reply to Andrew Beckett

Dear Andrew,

Thanks a lot. Could you please little bit more clear about before approach and approach you have talked about.

Kind Regards,
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Frank Wiedmann over 4 years ago in reply to RFStuff

Did you read the information at the link that Andrew mentioned? I find that pretty clear and detailed.
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Andrew Beckett over 4 years ago in reply to Frank Wiedmann

Thanks Frank. Indeed the "before" and "after" terms are simply referring to things mentioned in the linked article.

Andrew.
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RFStuff over 4 years ago in reply to Andrew Beckett

Thanks Andrew and Frank.

I went through the doc. and the terms are clearly explained.
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