[LVS Error] Missing ME1_PSUB via

Hi Karthik  

For such situations, you can use "Create->Multi-part path" or "Create->Fluid guardring" and check if there are PSUB templates from the foundry. If yes, you can then draw a guardring using the template and examine the required layers for creating PSUB to ME1 connection. If the templates are also not available, I guess you will need to check the PDK documents. : )


Best regards
Quek

Hi Quek !

First of all thank you so much for the response.
When i use Create -> MPP Guard ring , there are only 2 templates. N-tap and P-tap. The P-tap template creates a layer of P Diff around the instance. I do not see a "PSUB" template.

Can you give me a pointer as to what / where exactly I'm supposed to be looking in the FDK docs?
I am using UMC's 180nm FDK.

Thanks in advance!

Hi Karthik

The P-tap template is the one that you need.

Best regards
Quek

Hi Quek

I tried it out.

Before creating the p-tap guard ring or using a m1_pdiff via, these are the LVS errors

net mismatch, pin mismatch, rewire message.

After creating the p-tap guard ring, here are the LVS errors

net mismatch, pin mismatch

After replacing the p-tap guard ring with a m1_pdiff via, here are the LVS errors

pin mismatch


Given the color coding of the layers in the p-tap guard ring, I'd say it's taping the pdiff layer and not the psub layer (the color coding for the m1_pdiff via and the p-tap guard ring is the same)

How do i proceed?

Hi Karthik

If it is a "p-tap" guardring, I am surprised that there is still connection issue. I think it would be best for you to file a case in COS so that a Cadence AE from your local support centre can assist you with the issue. Without a testcase or a remote debugging session, it is hard to debug further.

LVS debugging cannot be based on the names of the categories (net mismatch, pin mismatch, etc). We have to look at the details of each section. When reporting LVS errors, it would be best for you to also post the LVS log file and report file.


Best regards
Quek

Hi Quek

After multiple failed attempts to resolve these LVS errors, I was able to clear them out as "errors" but some problems still exist.

Here is a screenshot of my layout.

Here is the concatenated content of those files (in the same order) displayed through the window after a successful LVS run.

Schematic                       | Layout                       | Status
-------------------------------------------------------------------------------
nand2 schematic lowpower-std    | nand2 layout lowpower-std    | errors      *

Mismatch between Schematic and Layout
   1 cell with errors
*******************************************************************************
****** nand2 schematic lowpower-std  <vs>  nand3 layout lowpower-std
*******************************************************************************

Pre-expand Statistics
======================                          Original
Cell/Device                               schematic  layout
(P_18_MM) MOS                                     2       2
(N_18_MM) MOS                                     2       2
                                             ------  ------
Total                                             4       4

Filter Statistics
=================                               Original            Filtered
Cell/Device                               schematic  layout   schematic  layout
(N_18_MM) MOS                                     2       2           2       2
(P_18_MM) MOS                                     2       2           2       2

Reduce Statistics
=================                               Filtered             Reduced
Cell/Device                               schematic  layout   schematic  layout
(N_18_MM) MOS                                     2       2           0       0
(P_18_MM) MOS                                     2       2           0       2*
(N_18_MM:SerMos2#1) MosBlk                        -       -           1       1
(P_18_MM:ParMos2#1, -) MosBlk                     -       -           1       -*

Match Statistics
================                                  Total             Unmatched
Cell/Device                               schematic  layout   schematic  layout
(N_18_MM) MOS                                     0       0           0       0
(P_18_MM) MOS                                     0       2*          0       2*
(N_18_MM:SerMos2#1) MosBlk                        1       1           0       0
(P_18_MM:ParMos2#1, -) MosBlk                     1       -*          1       -*
                                             ------  ------      ------  ------
Total                                             2       3           1       2

Match Statistics for Nets                         5       4           1       0

========================================================================[nand2]
====== Unmatched Pins =========================================================
===============================================================================

S ?Vdd

========================================================================[nand2]
====== Unbound Pin ============================================================
===============================================================================

S A
S B
S Y
S Vdd

========================================================================[nand2]
====== Bad Matched Nets (don't really match) ==================================
===============================================================================

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badmatch 1)
Schematic Net:  A
S       1   of N_18_MM:SerMos2#1 {IN1 IN2}
S      *1   of P_18_MM:ParMos2#1 {IN1 IN2}

Layout Net:  avC5
L      *1   of P_18_MM G
L       1   of N_18_MM:SerMos2#1 {IN1 IN2}

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badmatch 2)
Schematic Net:  B
S       1   of N_18_MM:SerMos2#1 {IN1 IN2}
S      *1   of P_18_MM:ParMos2#1 {IN1 IN2}

Layout Net:  avC4
L      *1   of P_18_MM G
L       1   of N_18_MM:SerMos2#1 {IN1 IN2}

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badmatch 3)
Schematic Net:  Y
S       1   of N_18_MM:SerMos2#1 {OUT OUT2}
S      *1   of P_18_MM:ParMos2#1 {OUT OUT2}

Layout Net:  avC2
L      *4   of P_18_MM {D S}
L      *2   of P_18_MM B
L       1   of N_18_MM:SerMos2#1 {OUT OUT2}

========================================================================[nand2]
====== Problem Schematic Nets (no exact match in layout) ======================
===============================================================================
S
S ?Y
S       1   of N_18_MM:SerMos2#1 {OUT OUT2}
S       1   of P_18_MM:ParMos2#1 {OUT OUT2}
S
S ?A ?B
S (total 2) with:
S       1   of N_18_MM:SerMos2#1 {IN1 IN2}
S       1   of P_18_MM:ParMos2#1 {IN1 IN2}
S
S ?Vdd
S       1   of P_18_MM:ParMos2#1 {OUT OUT2}
S       1   of P_18_MM:ParMos2#1 TERM4

========================================================================[nand2]
====== Problem Layout Nets (no exact match in schematic) ======================
===============================================================================
L
L ?avC5 ?avC4
L (total 2) with:
L       1   of P_18_MM G
L       1   of N_18_MM:SerMos2#1 {IN1 IN2}
L
L ?avC2
L       4   of P_18_MM {D S}
L       2   of P_18_MM B
L       1   of N_18_MM:SerMos2#1 {OUT OUT2}

========================================================================[nand2]
====== Unmatched Schematic Instances ==========================================
===============================================================================

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (schinst 1)
Schematic Instance: I##6  P_18_MM:ParMos2#1

S Pin        Net
S ---        ---
S OUT        Y
S OUT2       ?Vdd
S TERM4      ?Vdd
S IN1        A
S IN2        B

========================================================================[nand2]
====== Unmatched Layout Instances =============================================
===============================================================================

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (layinst 1)
Layout Instance:    avD28_1  P_18_MM

L Pin        Net
L ---        ---
L D          Y
L G          A
L S          Y
L B          Y

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (layinst 2)
Layout Instance:    avD28_2  P_18_MM

L Pin        Net
L ---        ---
L D          Y
L G          B
L S          Y
L B          Y

========================================================================[nand2]
====== Summary of Errors ======================================================
===============================================================================

Schematic  Layout     Error Type
---------  ------     ----------
 1          -         Unmatched Pins
 3          3         Bad Matched Nets
 1          2         Unmatched Instances
 4          -         Unbound Pin


; autoPinSwap() results for schematic network.

I'm not 100% sure if those substrate connections are correct, but if they're not, then There is a 'psubStampErrorFloat' when I remove the substrate drawing with the M1_PDIFF via (nmos ground connection to the substrate) and a 'nwelStampErrorFloat' if I make the pmos substrate connection in pretty much any other manner.

How do I go about this? My COS account is not entitled to create cases (I was given a reference key by my university and not a Host ID).

Hi Karthik

In general, COS accounts are not given to university students as they are expected to file cases through their lecturers or CAD admins.

It seems that you do not have any layout pins. Would you please add the appropriate labels? E.g. add label "A" using "M1_CAD/TEXT" layer on any shape that belongs to net "A".


Best regards
Quek

Hi Karthik

In general, COS accounts are not given to university students as they are expected to file cases through their lecturers or CAD admins.

It seems that you do not have any layout pins. Would you please add the appropriate labels? E.g. add label "A" using "M1_CAD/TEXT" layer on any shape that belongs to net "A".


Best regards
Quek

Hi, this issue was resolved.
I read the drc and lvs rule files and it seems like the psub layer is not referenced directly. this means an m1_psub via is actually not missing, but was never meant to be there.
The drc errors were resolved by snapping the m1_pdiff via to the body of the nmos.

thanks!