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compare two netlists

sjwprcker
sjwprcker over 4 years ago

Hi, 

I need to compare two netlists frequently, one is old netlist, one is new netlist. Suppose only several updates have been done in the design, meaning 99% of netlists should be the same.

But when i compare two netlists by tkdiff command, i find many cells sequence is changed, although the content is the same. As designer it is quite annoying to locate the difference between two netlists. 

So I wanna to understand the rule of netlist creation, and is there anyway to force spectre netlist not changing cells sequence?

Or virtuoso has any other way to compare two design efficiently?

BR

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  • Andrew Beckett
    Andrew Beckett over 4 years ago

    For efficiency reasons, the netlists are produced in the order that is returned from the database - and given that edits to the schematic can result in that "order" changing (it's not really ordered), the sequence of instances can be altered. The same is true of the order of the blocks being netlisted too - that expansion order can depend on the order of the instances.

    There are no controls provided (as far as I know) to change this, because generally it should not matter. The netlister is not designed to allow you to do simple text-based differences because that would be rarely useful.

    If you are trying to compare netlists, you should use a schematic-versus-schematic (SVS) tool, such as PVS provides.

    Regards,

    Andrew.

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  • ShawnLogan
    ShawnLogan over 4 years ago in reply to Andrew Beckett

    Dear sjwprckr,

    As an alternative to performing a comparison using, for example, an LVS comparison in line with Andrew's (as usual very prompt!) suggestion, two possible alternatives.

    1. From the CIW, export each schematic to a common format and specifically EDIF format from its File menu as shown in Figure 1. I tried this for two schematics whose connectivity was identical, but whose wires were on different schematic grids. Using the following UNIX command to filter out the differences in the schematic positions between the two schematics, I was able to verify the two were identical from a component perspective:

    diff ./v1p6/edif.out ./v1p5/edif.out | grep -v transform | grep -v origin | grep -v pt > compare_edif.txt

    tkdiff mat be used, as you did, to graphically display the differences.

    2. There is a company called Elgris that provides tools for the comparison of netlists (estudio). I have not personally tried their tool, but they specialize in cross-platform analysis of various input data formats.

    I hope these two thoughts help a little too!

    Shawn

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  • MaximX
    MaximX over 4 years ago in reply to ShawnLogan

    Another common need is a comparison of two post-layout netlists (without running full-blown post-layout SPICE or any other simulation)  - to compare different layout revisions (and their impact on circuit and parasitics), different versions of PDK, LVS tool, extraction tool, extraction settings (e.g. with / without floating metal fill), etc.

    That's a much trickier thing than comparing schematic netlists...

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