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NPORT compression "not working"

TommasoF

Hi all,

until now I was simulating with a SP file which was compressed during the simulation, like the log files shows 

**********************************************************************************************************************************

Reading file: /projects/ibm/csoi8sw/QM77180/work_libs/tfant/cds/04_snp/es2lam_evb/v10_reduced.s542p


Notice from spectre during hierarchy flattening.
nport instance NPORT0 has 348 unused ports formed between: (HBLNA1_OMN_block_se, 0),(HBLNA1_OMN_Ctune, 0),(HBLNA1_OMN_Decoup0, 0),(HBLNA1_OMN_Decoup1, 0),(HBLNA1_OMN_Decoup2, 0),(HBLNA1_OMN_ESD, 0),(HBLNA1_OMN_Ldrain, 0),(HBLNA1_OMN_vddRes, 0),(HBLNA1_unit1_byp_C1, 0),(HBLNA1_unit1_byp_C2, 0),(HBLNA1_unit1_byp_se1, 0),(HBLNA1_unit1_byp_se2, 0),(HBLNA1_unit1_byp_sh, 0),(HBLNA1_unit1_cg_ds, 0),(HBLNA1_unit1_cg_gs, 0),(HBLNA1_unit1_cgbias_C, 0),(HBLNA1_unit1_cgbias_CR, 0),(HBLNA1_unit1_cgbias_iref, 0),(HBLNA1_unit1_cgbias_res, 0),(HBLNA1_unit1_cgbias_vbias, 0),(HBLNA1_unit1_Cs, 0),(HBLNA1_unit1_cs_ds, 0),(HBLNA1_unit1_cs_gs, 0),(HBLNA1_unit1_csbias_C, 0),(HBLNA1_unit1_csbias_cg_iref, 0),(HBLNA1_unit1_csbias_cs_iref, 0),(HBLNA1_unit1_csbias_R, 0),(HBLNA1_unit1_csbias_vbias, 0),(HBLNA1_unit1_drainZ, 0),(HBLNA1_unit1_inputSH_ESD, 0),(HBLNA1_unit2_byp_C1, 0),(HBLNA1_unit2_byp_C2, 0),(HBLNA1_unit2_byp_se1, 0),(HBLNA1_unit2_byp_se2, 0),(HBLNA1_unit2_byp_sh, 0),(HBLNA1_unit2_cg_ds, 0),(HBLNA1_unit2_cg_gs, 0),(HBLNA1_unit2_cgbias_C, 0),(HBLNA1_unit2_cgbias_CR, 0),(HBLNA1_unit2_cgbias_iref, 0),(HBLNA1_unit2_cgbias_res, 0),(HBLNA1_unit2_cgbias_vbias, 0),(HBLNA1_unit2_Cs, 0),(HBLNA1_unit2_cs_ds, 0),(HBLNA1_unit2_cs_gs, 0),(HBLNA1_unit2_csbias_C, 0),(HBLNA1_unit2_csbias_cg_iref, 0),(HBLNA1_unit2_csbias_cs_iref, 0),(HBLNA1_unit2_csbias_R, 0),(HBLNA1_unit2_csbias_vbias, 0),(HBLNA1_unit2_drainZ, 0),(HBLNA1_unit2_inputSH_ESD, 0),(HBLNA1_unit3_byp_C1, 0),(HBLNA1_unit3_byp_C2, 0),(HBLNA1_unit3_byp_se1, 0),(HBLNA1_unit3_byp_se2, 0),(HBLNA1_unit3_byp_sh, 0),(HBLNA1_unit3_cg_ds, 0),(HBLNA1_unit3_cg_gs, 0),(HBLNA1_unit3_cgbias_C, 0),(HBLNA1_unit3_cgbias_cg_iref, 0),(HBLNA1_unit3_cgbias_res, 0),(HBLNA1_unit3_Cs, 0),(HBLNA1_unit3_cs_ds, 0),(HBLNA1_unit3_cs_gs, 0),(HBLNA1_unit3_csbias_C, 0),(HBLNA1_unit3_csbias_cg_iref, 0),(HBLNA1_unit3_csbias_cs_iref, 0),(HBLNA1_unit3_csbias_vbias, 0),(HBLNA1_unit3_drainZ, 0),(HBLNA1_unit3_inputSH_ESD, 0),(HBLNA1_unit3_Ldeg, 0),(HBLNA1_unit12_Ldeg, 0),(MBLNA1_OMN_block_se, 0),(MBLNA1_OMN_Ctune, 0),(MBLNA1_OMN_Decoup0, 0),(MBLNA1_OMN_Decoup1, 0),(MBLNA1_OMN_Decoup2, 0),(MBLNA1_OMN_drain_res, 0),(MBLNA1_OMN_ESD, 0),(MBLNA1_OMN_Ldrain, 0),(MBLNA1_OMN_vddRes, 0),(MBLNA1_unit1_byp_C1, 0),(MBLNA1_unit1_byp_C2, 0),(MBLNA1_unit1_byp_se1, 0),(MBLNA1_unit1_byp_se2, 0),(MBLNA1_unit1_byp_sh, 0),(MBLNA1_unit1_cg_ds, 0),(MBLNA1_unit1_cg_gs, 0),(MBLNA1_unit1_cgbias_C, 0),(MBLNA1_unit1_cgbias_CR, 0),(MBLNA1_unit1_cgbias_iref, 0),(MBLNA1_unit1_cgbias_res, 0),(MBLNA1_unit1_cgbias_vbias, 0),(MBLNA1_unit1_Cs, 0),(MBLNA1_unit1_cs_ds, 0),(MBLNA1_unit1_cs_gs, 0),(MBLNA1_unit1_csbias_C, 0),(MBLNA1_unit1_csbias_cg_iref, 0),(MBLNA1_unit1_csbias_cs_iref, 0),(MBLNA1_unit1_csbias_R, 0),(MBLNA1_unit1_csbias_vbias, 0),(MBLNA1_unit1_drainZ, 0),(MBLNA1_unit1_inputSH_ESD, 0),(MBLNA1_unit2_byp_C1, 0),(MBLNA1_unit2_byp_C2, 0),(MBLNA1_unit2_byp_se1, 0),(MBLNA1_unit2_byp_se2, 0),(MBLNA1_unit2_byp_sh, 0),(MBLNA1_unit2_cg_ds, 0),(MBLNA1_unit2_cg_gs, 0),(MBLNA1_unit2_cgbias_C, 0),(MBLNA1_unit2_cgbias_CR, 0),(MBLNA1_unit2_cgbias_iref, 0),(MBLNA1_unit2_cgbias_res, 0),(MBLNA1_unit2_cgbias_vbias, 0),(MBLNA1_unit2_Cs, 0),(MBLNA1_unit2_cs_ds, 0),(MBLNA1_unit2_cs_gs, 0),(MBLNA1_unit2_csbias_C, 0),(MBLNA1_unit2_csbias_cg_iref, 0),(MBLNA1_unit2_csbias_cs_iref, 0),(MBLNA1_unit2_csbias_R, 0),(MBLNA1_unit2_csbias_vbias, 0),(MBLNA1_unit2_drainZ, 0),(MBLNA1_unit2_inputSH_ESD, 0),(MBLNA1_unit3_byp_C1, 0),(MBLNA1_unit3_byp_C2, 0),(MBLNA1_unit3_byp_se1, 0),(MBLNA1_unit3_byp_se2, 0),(MBLNA1_unit3_byp_sh, 0),(MBLNA1_unit3_cg_ds, 0),(MBLNA1_unit3_cg_gs, 0),(MBLNA1_unit3_cgbias_C, 0),(MBLNA1_unit3_cgbias_cg_iref, 0),(MBLNA1_unit3_cgbias_res, 0),(MBLNA1_unit3_Cs, 0),(MBLNA1_unit3_cs_ds, 0),(MBLNA1_unit3_cs_gs, 0),(MBLNA1_unit3_csbias_C, 0),(MBLNA1_unit3_csbias_cg_iref, 0),(MBLNA1_unit3_csbias_cs_iref, 0),(MBLNA1_unit3_csbias_vbias, 0),(MBLNA1_unit3_drainZ, 0),(MBLNA1_unit3_inputSH_ESD, 0),(MBLNA1_unit3_Ldeg, 0),(MBLNA1_unit12_Ldeg, 0),(MBLNA2_OMN_block_se, 0),(MBLNA2_OMN_Ctune, 0),(MBLNA2_OMN_Decoup0, 0),(MBLNA2_OMN_Decoup1, 0),(MBLNA2_OMN_Decoup2, 0),(MBLNA2_OMN_drain_res, 0),(MBLNA2_OMN_ESD, 0),(MBLNA2_OMN_Ldrain, 0),(MBLNA2_OMN_vddRes, 0),(MBLNA2_unit1_byp_C1, 0),(MBLNA2_unit1_byp_C2, 0),(MBLNA2_unit1_byp_se1, 0),(MBLNA2_unit1_byp_se2, 0),(MBLNA2_unit1_byp_sh, 0),(MBLNA2_unit1_cg_ds, 0),(MBLNA2_unit1_cg_gs, 0),(MBLNA2_unit1_cgbias_C, 0),(MBLNA2_unit1_cgbias_CR, 0),(MBLNA2_unit1_cgbias_iref, 0),(MBLNA2_unit1_cgbias_res, 0),(MBLNA2_unit1_cgbias_vbias, 0),(MBLNA2_unit1_Cs, 0),(MBLNA2_unit1_cs_ds, 0),(MBLNA2_unit1_cs_gs, 0),(MBLNA2_unit1_csbias_C, 0),(MBLNA2_unit1_csbias_cg_iref, 0),(MBLNA2_unit1_csbias_cs_iref, 0),(MBLNA2_unit1_csbias_R, 0),(MBLNA2_unit1_csbias_vbias, 0),(MBLNA2_unit1_drainZ, 0),(MBLNA2_unit1_inputSH_ESD, 0),(MBLNA2_unit2_byp_C1, 0),(MBLNA2_unit2_byp_C2, 0),(MBLNA2_unit2_byp_se1, 0),(MBLNA2_unit2_byp_se2, 0),(MBLNA2_unit2_byp_sh, 0),(MBLNA2_unit2_cg_ds, 0),(MBLNA2_unit2_cg_gs, 0),(MBLNA2_unit2_cgbias_C, 0),(MBLNA2_unit2_cgbias_CR, 0),(MBLNA2_unit2_cgbias_iref, 0),(MBLNA2_unit2_cgbias_res, 0),(MBLNA2_unit2_cgbias_vbias, 0),(MBLNA2_unit2_Cs, 0),(MBLNA2_unit2_cs_ds, 0),(MBLNA2_unit2_cs_gs, 0),(MBLNA2_unit2_csbias_C, 0),(MBLNA2_unit2_csbias_cg_iref, 0),(MBLNA2_unit2_csbias_cs_iref, 0),(MBLNA2_unit2_csbias_R, 0),(MBLNA2_unit2_csbias_vbias, 0),(MBLNA2_unit2_drainZ, 0),(MBLNA2_unit2_inputSH_ESD, 0),(MBLNA2_unit3_byp_C1, 0),(MBLNA2_unit3_byp_C2, 0),(MBLNA2_unit3_byp_se1, 0),(MBLNA2_unit3_byp_se2, 0),(MBLNA2_unit3_byp_sh, 0),(MBLNA2_unit3_cg_ds, 0),(MBLNA2_unit3_cg_gs, 0),(MBLNA2_unit3_cgbias_C, 0),(MBLNA2_unit3_cgbias_cg_iref, 0),(MBLNA2_unit3_cgbias_res, 0),(MBLNA2_unit3_Cs, 0),(MBLNA2_unit3_cs_ds, 0),(MBLNA2_unit3_cs_gs, 0),(MBLNA2_unit3_csbias_C, 0),(MBLNA2_unit3_csbias_cg_iref, 0),(MBLNA2_unit3_csbias_cs_iref, 0),(MBLNA2_unit3_csbias_vbias, 0),(MBLNA2_unit3_drainZ, 0),(MBLNA2_unit3_inputSH_ESD, 0),(MBLNA2_unit3_Ldeg, 0),(MBLNA2_unit12_Ldeg, 0),(MBLNA3_OMN_block_se, 0),(MBLNA3_OMN_Ctune, 0),(MBLNA3_OMN_Decoup0, 0),(MBLNA3_OMN_Decoup1, 0),(MBLNA3_OMN_Decoup2, 0),(MBLNA3_OMN_ESD, 0),(MBLNA3_OMN_Ldrain, 0),(MBLNA3_OMN_vddRes, 0),(MBLNA3_unit1_byp_C1, 0),(MBLNA3_unit1_byp_C2, 0),(MBLNA3_unit1_byp_se1, 0),(MBLNA3_unit1_byp_se2, 0),(MBLNA3_unit1_byp_sh, 0),(MBLNA3_unit1_cg_ds, 0),(MBLNA3_unit1_cg_gs, 0),(MBLNA3_unit1_cgbias_C, 0),(MBLNA3_unit1_cgbias_CR, 0),(MBLNA3_unit1_cgbias_iref, 0),(MBLNA3_unit1_cgbias_res, 0),(MBLNA3_unit1_cgbias_vbias, 0),(MBLNA3_unit1_Cs, 0),(MBLNA3_unit1_cs_ds, 0),(MBLNA3_unit1_cs_gs, 0),(MBLNA3_unit1_csbias_C, 0),(MBLNA3_unit1_csbias_cg_iref, 0),(MBLNA3_unit1_csbias_cs_iref, 0),(MBLNA3_unit1_csbias_R, 0),(MBLNA3_unit1_csbias_vbias, 0),(MBLNA3_unit1_drainZ, 0),(MBLNA3_unit1_inputSH_ESD, 0),(MBLNA3_unit2_byp_C1, 0),(MBLNA3_unit2_byp_C2, 0),(MBLNA3_unit2_byp_se1, 0),(MBLNA3_unit2_byp_se2, 0),(MBLNA3_unit2_byp_sh, 0),(MBLNA3_unit2_cg_ds, 0),(MBLNA3_unit2_cg_gs, 0),(MBLNA3_unit2_cgbias_C, 0),(MBLNA3_unit2_cgbias_CR, 0),(MBLNA3_unit2_cgbias_iref, 0),(MBLNA3_unit2_cgbias_res, 0),(MBLNA3_unit2_cgbias_vbias, 0),(MBLNA3_unit2_Cs, 0),(MBLNA3_unit2_cs_ds, 0),(MBLNA3_unit2_cs_gs, 0),(MBLNA3_unit2_csbias_C, 0),(MBLNA3_unit2_csbias_cg_iref, 0),(MBLNA3_unit2_csbias_cs_iref, 0),(MBLNA3_unit2_csbias_R, 0),(MBLNA3_unit2_csbias_vbias, 0),(MBLNA3_unit2_drainZ, 0),(MBLNA3_unit2_inputSH_ESD, 0),(MBLNA3_unit3_byp_C1, 0),(MBLNA3_unit3_byp_C2, 0),(MBLNA3_unit3_byp_se1, 0),(MBLNA3_unit3_byp_se2, 0),(MBLNA3_unit3_byp_sh, 0),(MBLNA3_unit3_cg_ds, 0),(MBLNA3_unit3_cg_gs, 0),(MBLNA3_unit3_cgbias_C, 0),(MBLNA3_unit3_cgbias_cg_iref, 0),(MBLNA3_unit3_cgbias_res, 0),(MBLNA3_unit3_Cs, 0),(MBLNA3_unit3_cs_ds, 0),(MBLNA3_unit3_cs_gs, 0),(MBLNA3_unit3_csbias_C, 0),(MBLNA3_unit3_csbias_cg_iref, 0),(MBLNA3_unit3_csbias_cs_iref, 0),(MBLNA3_unit3_csbias_vbias, 0),(MBLNA3_unit3_drainZ, 0),(MBLNA3_unit3_inputSH_ESD, 0),(MBLNA3_unit3_Ldeg, 0),(MBLNA3_unit12_Ldeg, 0),(MLBLNA_OMN_block_se, 0),(MLBLNA_OMN_Ctune, 0),(MLBLNA_OMN_Decoup0, 0),(MLBLNA_OMN_Decoup1, 0),(MLBLNA_OMN_ESD, 0),(MLBLNA_OMN_Ldrain, 0),(MLBLNA_OMN_vddRes, 0),(MLBLNA_unit1_byp_C1, 0),(MLBLNA_unit1_byp_C2, 0),(MLBLNA_unit1_byp_se1, 0),(MLBLNA_unit1_byp_se2, 0),(MLBLNA_unit1_byp_sh, 0),(MLBLNA_unit1_cg_ds, 0),(MLBLNA_unit1_cg_gs, 0),(MLBLNA_unit1_cgbias_C, 0),(MLBLNA_unit1_cgbias_CR, 0),(MLBLNA_unit1_cgbias_iref, 0),(MLBLNA_unit1_cgbias_res, 0),(MLBLNA_unit1_cgbias_vbias, 0),(MLBLNA_unit1_Cs, 0),(MLBLNA_unit1_cs_ds, 0),(MLBLNA_unit1_cs_gs, 0),(MLBLNA_unit1_csbias_C, 0),(MLBLNA_unit1_csbias_cg_iref, 0),(MLBLNA_unit1_csbias_cs_iref, 0),(MLBLNA_unit1_csbias_R, 0),(MLBLNA_unit1_csbias_vbias, 0),(MLBLNA_unit1_drainZ, 0),(MLBLNA_unit1_inputSH_ESD, 0),(MLBLNA_unit2_byp_C1, 0),(MLBLNA_unit2_byp_C2, 0),(MLBLNA_unit2_byp_se1, 0),(MLBLNA_unit2_byp_se2, 0),(MLBLNA_unit2_byp_sh, 0),(MLBLNA_unit2_cg_ds, 0),(MLBLNA_unit2_cg_gs, 0),(MLBLNA_unit2_cgbias_C, 0),(MLBLNA_unit2_cgbias_CR, 0),(MLBLNA_unit2_cgbias_iref, 0),(MLBLNA_unit2_cgbias_res, 0),(MLBLNA_unit2_cgbias_vbias, 0),(MLBLNA_unit2_Cs, 0),(MLBLNA_unit2_cs_ds, 0),(MLBLNA_unit2_cs_gs, 0),(MLBLNA_unit2_csbias_C, 0),(MLBLNA_unit2_csbias_cg_iref, 0),(MLBLNA_unit2_csbias_cs_iref, 0),(MLBLNA_unit2_csbias_R, 0),(MLBLNA_unit2_csbias_vbias, 0),(MLBLNA_unit2_drainZ, 0),(MLBLNA_unit2_inputSH_ESD, 0),(MLBLNA_unit12_Ldeg, 0),(0, 0),(0, 0).
To make the simulation more efficient, original S-parameters data file
/projects/ibm/csoi8sw/QM77180/work_libs/tfant/cds/04_snp/es2lam_evb/v10_reduced.s542p
has been compressed to
/scratch/tfant/simulation/QM77180_tb/tb_em_fullchip_v3/maestro/results/maestro/Interactive.75/1/die01_hb2/netlist/v10_reduced_compressed_1.s194p
with no loss of accuracy. This operation is equivalent to replacing, in the flat version of the netlist, the original instance line with the following:
NPORT0( 4000A_EVB_EM_LNA_v2_LNA_AUX_1 0 4000A_EVB_EM_LNA_v2_LNA_AUX_2 0 4000A_EVB_EM_LNA_v2_LNA_AUX_3 0 4000A_EVB_EM_LNA_v2_LNA_AUX_4 0 4000A_EVB_EM_LNA_v2_LNA_AUX_LMB 0 4000A_EVB_EM_LNA_v2_LNA_AUX_MB 0 HBLNA1_unit1_csbias_cg_iref_IDAC 0 HBLNA1_unit1_csbias_cs_iref_IDAC 0 HBLNA1_unit2_csbias_cg_iref_IDAC 0 HBLNA1_unit2_csbias_cs_iref_IDAC 0 HBLNA1_unit3_csbias_cg_iref_IDAC 0 HBLNA1_unit3_csbias_cs_iref_IDAC 0 HBLNA2_OMN_block_se 0 HBLNA2_OMN_Ctune 0 HBLNA2_OMN_Decoup0 0 HBLNA2_OMN_Decoup1 0 HBLNA2_OMN_ESD 0 HBLNA2_OMN_Ldrain 0 HBLNA2_OMN_vddRes 0 HBLNA2_unit1_byp_C1 0 HBLNA2_unit1_byp_C2 0 HBLNA2_unit1_byp_se1 0 HBLNA2_unit1_byp_se2 0 HBLNA2_unit1_byp_sh 0 HBLNA2_unit1_cg_ds 0 HBLNA2_unit1_cg_gs 0 HBLNA2_unit1_cgbias_C 0 HBLNA2_unit1_cgbias_CR 0 HBLNA2_unit1_cgbias_iref 0 HBLNA2_unit1_cgbias_res 0 HBLNA2_unit1_cgbias_vbias 0 HBLNA2_unit1_Cs 0 HBLNA2_unit1_cs_ds 0 HBLNA2_unit1_cs_gs 0 HBLNA2_unit1_csbias_C 0 HBLNA2_unit1_csbias_cg_iref 0 HBLNA2_unit1_csbias_cg_iref_IDAC 0 HBLNA2_unit1_csbias_cs_iref 0 HBLNA2_unit1_csbias_cs_iref_IDAC 0 HBLNA2_unit1_csbias_R 0 HBLNA2_unit1_csbias_vbias 0 HBLNA2_unit1_drainZ 0 HBLNA2_unit1_inputSH_ESD 0 HBLNA2_unit2_byp_C1 0 HBLNA2_unit2_byp_C2 0 HBLNA2_unit2_byp_se1 0 HBLNA2_unit2_byp_se2 0 HBLNA2_unit2_byp_sh 0 HBLNA2_unit2_cg_ds 0 HBLNA2_unit2_cg_gs 0 HBLNA2_unit2_cgbias_C 0 HBLNA2_unit2_cgbias_CR 0 HBLNA2_unit2_cgbias_iref 0 HBLNA2_unit2_cgbias_res 0 HBLNA2_unit2_cgbias_vbias 0 HBLNA2_unit2_Cs 0 HBLNA2_unit2_cs_ds 0 HBLNA2_unit2_cs_gs 0 HBLNA2_unit2_csbias_C 0 HBLNA2_unit2_csbias_cg_iref 0 HBLNA2_unit2_csbias_cg_iref_IDAC 0 HBLNA2_unit2_csbias_cs_iref 0 HBLNA2_unit2_csbias_cs_iref_IDAC 0 HBLNA2_unit2_csbias_R 0 HBLNA2_unit2_csbias_vbias 0 HBLNA2_unit2_drainZ 0 HBLNA2_unit2_inputSH_ESD 0 HBLNA2_unit12_Ldeg 0 MBLNA1_unit1_csbias_cg_iref_IDAC 0 MBLNA1_unit1_csbias_cs_iref_IDAC 0 MBLNA1_unit2_csbias_cg_iref_IDAC 0 MBLNA1_unit2_csbias_cs_iref_IDAC 0 MBLNA1_unit3_csbias_cg_iref_IDAC 0 MBLNA1_unit3_csbias_cs_iref_IDAC 0 MBLNA2_unit1_csbias_cg_iref_IDAC 0 MBLNA2_unit1_csbias_cs_iref_IDAC 0 MBLNA2_unit2_csbias_cg_iref_IDAC 0 MBLNA2_unit2_csbias_cs_iref_IDAC 0 MBLNA2_unit3_csbias_cg_iref_IDAC 0 MBLNA2_unit3_csbias_cs_iref_IDAC 0 MBLNA3_unit1_csbias_cg_iref_IDAC 0 MBLNA3_unit1_csbias_cs_iref_IDAC 0 MBLNA3_unit2_csbias_cg_iref_IDAC 0 MBLNA3_unit2_csbias_cs_iref_IDAC 0 MBLNA3_unit3_csbias_cg_iref_IDAC 0 MBLNA3_unit3_csbias_cs_iref_IDAC 0 MLBLNA_unit1_csbias_cg_iref_IDAC 0 MLBLNA_unit1_csbias_cs_iref_IDAC 0 MLBLNA_unit2_csbias_cg_iref_IDAC 0 MLBLNA_unit2_csbias_cs_iref_IDAC 0 MUX_HB1_OUT1_se1 0 MUX_HB1_OUT1_se2 0 MUX_HB1_OUT1_sh 0 MUX_HB1_OUT2_se1 0 MUX_HB1_OUT2_se2 0 MUX_HB1_OUT2_sh 0 MUX_HB1_OUT3_se1 0 MUX_HB1_OUT3_se2 0 MUX_HB1_OUT3_sh 0 MUX_HB1_OUT4_se1 0 MUX_HB1_OUT4_se2 0 MUX_HB1_OUT4_sh 0 MUX_HB2_OUT1_se1 0 MUX_HB2_OUT1_se2 0 MUX_HB2_OUT1_sh 0 MUX_HB2_OUT2_se1 0 MUX_HB2_OUT2_se2 0 MUX_HB2_OUT2_sh 0 MUX_HB2_OUT3_se1 0 MUX_HB2_OUT3_se2 0 MUX_HB2_OUT3_sh 0 MUX_HB2_OUT4_se1 0 MUX_HB2_OUT4_se2 0 MUX_HB2_OUT4_sh 0 MUX_LMB_OUT1_se1 0 MUX_LMB_OUT1_se2 0 MUX_LMB_OUT1_sh 0 MUX_LMB_OUT2_se1 0 MUX_LMB_OUT2_se2 0 MUX_LMB_OUT2_sh 0 MUX_LMB_OUT3_se1 0 MUX_LMB_OUT3_se2 0 MUX_LMB_OUT3_sh 0 MUX_LMB_OUT4_se1 0 MUX_LMB_OUT4_se2 0 MUX_LMB_OUT4_sh 0 MUX_MB1_OUT1_se1 0 MUX_MB1_OUT1_se2 0 MUX_MB1_OUT1_sh 0 MUX_MB1_OUT2_se1 0 MUX_MB1_OUT2_se2 0 MUX_MB1_OUT2_sh 0 MUX_MB1_OUT3_se1 0 MUX_MB1_OUT3_se2 0 MUX_MB1_OUT3_sh 0 MUX_MB1_OUT4_se1 0 MUX_MB1_OUT4_se2 0 MUX_MB1_OUT4_sh 0 MUX_MB2_OUT1_se1 0 MUX_MB2_OUT1_se2 0 MUX_MB2_OUT1_sh 0 MUX_MB2_OUT2_se1 0 MUX_MB2_OUT2_se2 0 MUX_MB2_OUT2_sh 0 MUX_MB2_OUT3_se1 0 MUX_MB2_OUT3_se2 0 MUX_MB2_OUT3_sh 0 MUX_MB2_OUT4_se1 0 MUX_MB2_OUT4_se2 0 MUX_MB2_OUT4_sh 0 MUX_MB3_OUT1_se1 0 MUX_MB3_OUT1_se2 0 MUX_MB3_OUT1_sh 0 MUX_MB3_OUT2_se1 0 MUX_MB3_OUT2_se2 0 MUX_MB3_OUT2_sh 0 MUX_MB3_OUT3_se1 0 MUX_MB3_OUT3_se2 0 MUX_MB3_OUT3_sh 0 MUX_MB3_OUT4_se1 0 MUX_MB3_OUT4_se2 0 MUX_MB3_OUT4_sh 0 MUX_OUT1_Cs 0 MUX_OUT1_ESD 0 OUT4_MUX_0p5dBattn_res_in 0 OUT4_MUX_0p5dBattn_res_out 0 OUT4_MUX_0p5dBattn_se 0 OUT4_MUX_0p5dBattn_sh 0 OUT4_MUX_3dBattn_res_in 0 OUT4_MUX_3dBattn_res_out 0 OUT4_MUX_3dBattn_se 0 OUT4_MUX_3dBattn_sh 0 VDDDAC_cap 0 VDDDAC_HB1 0 VDDDAC_HB2 0 VDDDAC_MB1 0 VDDDAC_MB2 0 VDDDAC_MB3 0 VDDDAC_MLB 0 lam__001_LNA_U24_VDD 0 lam__087_LNA_U24_B1 0 lam__088_LNA_U24_B3 0 lam__089_LNA_U24_B4 0 lam__090_LNA_U24_B7 0 lam__091_LNA_U24_B25 0 lam__092_LNA_U24_B30 0 lam__093_LNA_U24_B34 0 lam__094_LNA_U24_B39 0 lam__095_LNA_U24_B40 0 lam__096_LNA_U24_B41 0 lam__097_LNA_U24_B70 0 lam__099_LNA_U24_B41H 0 lam__100_LNA_U24_B66R2 0 lam__102_LNA_U24_n75 0 ) nport file="/scratch/tfant/simulation/xxxxxx_tb/tb_em_fullchip_v3/maestro/results/maestro/Interactive.75/1/die01_hb2/netlist/v10_reduced_compressed_1.s194p" datafmt=touchstone,
while keeping the remaining instance parameter intact. In the current implementation, the voltages at the nodes that form the unused ports is set to zero. If you would like to turn this feature off, set the global option nportcompress to no.

**********************************************************************************************************************************

after having replaced the snp with a newly generated one and having edited some connections, the SP file is no longer compressed and the log file does not explain why. Is there a way to troubleshoot that ?

I tried several option (enable diagnostic, increase max warnings..) but it does not help. Also with the new Snp file most of the pots are unused, should it should be compressed.

thanks

Tommaso

Parents

  • Tommaso,

    The compression is done internally, to simplify the s-parameters to just the connected ports - which means that any resulting time-domain model (be it rational-based using bbspice or convolution-based using linear/spline) only has to be produced on this smaller s-parameter file. I don't know why you would attempt to use the reduced s-parameter file directly - that makes no sense. Also, if you had gone through (a fairly painful) effort of connecting up the reduced/compressed file, presumably all the ports would be connected up and so I wouldn't expect it to do further compression.

    So:

    1. Why are you trying to use the result of some internally generated file yourself - this seems rather bizarre to me?
    2. I would have expected that if there were even more ports that are unused, these would have been compressed too - it sounds as if your secondary setup has different connections than the original?

    Finally, debugging this via the forums is not the best way of doing this, because it would be rather important to see the data. Dealing with huge (542) port-count s-parameters typically requires some expertise, and you would be best to contact customer support.

    Andrew

Reply

  • Tommaso,

    The compression is done internally, to simplify the s-parameters to just the connected ports - which means that any resulting time-domain model (be it rational-based using bbspice or convolution-based using linear/spline) only has to be produced on this smaller s-parameter file. I don't know why you would attempt to use the reduced s-parameter file directly - that makes no sense. Also, if you had gone through (a fairly painful) effort of connecting up the reduced/compressed file, presumably all the ports would be connected up and so I wouldn't expect it to do further compression.

    So:

    1. Why are you trying to use the result of some internally generated file yourself - this seems rather bizarre to me?
    2. I would have expected that if there were even more ports that are unused, these would have been compressed too - it sounds as if your secondary setup has different connections than the original?

    Finally, debugging this via the forums is not the best way of doing this, because it would be rather important to see the data. Dealing with huge (542) port-count s-parameters typically requires some expertise, and you would be best to contact customer support.

    Andrew

Children
  • in reply to Andrew Beckett

    Hi Andrew,

    see my answer here

    1. Why are you trying to use the result of some internally generated file yourself - this seems rather bizarre to me? indeed I don't, I just desire that Spectre compress the file, but since it doesn't I have to run the sim with 542 ports
    2. I would have expected that if there were even more ports that are unused, these would have been compressed too - it sounds as if your secondary setup has different connections than the original? yes in the secondary setup I changed the snp file with the one I got back from the EM sim, updated 10 connections or so and that's it. I am not doing anything fancy, just changed file and re-simulate basically. Yes I imagine that doing that here it's not straightforward, I was just hoping there was a way to understand why spectre does not compress the file. Let me see how far I get otherwise I'll open a ticket. thank you Andrew
  • in reply to TommasoF

    Hi Andrew,
    I have opened a ticket.
    I did also a couple of test and so I took one of the snp files that is usually compressed and pasted into an empty schematic leaving all terminals open but one, where I tied a port component (50 ohm basically). Interestingly,  this snp that was previously compressed, now is no longer compressed, even though I have 1 terminal out of 542 connected. Maybe it depends also on the circuit complexity ? 
    Anyhow it seems not only depending on how many port are connected (like stated in the GUI of the analog option), but maybe also from other factors ?

    thanks

    Tommaso

  • in reply to TommasoF

    Hi Tommaso,

    I see one of my colleagues has picked up your case. I believe that the compression should occur if the ports are left unconnected or are shorted to ground (provided that fewer than 80% of the ports are used), so it would seem to meet the criteria. I'll leave it to my colleague to investigate (you probably will need to provide the s-parameter file and info on how it is connected up, BTW).

    Regards,

    Andrew

  • in reply to Andrew Beckett

    Hi Andrew,
    indeed, that would be my expectation as well. Yes I'll provide the snp when requested.

    thanks.
    BR,
    Tommaso

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