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[ Liberate ] Cells do not have -extsim_model parameter specified in define_leafcell command

iamKarthikBK

I am trying to characterize a standard cell library, but liberate gives me the following errors.

WARNING (LIB-40): (set_var): Ignored the invalid value '$model' specified for 'extsim_model_include'. It should be set to an absolute file path.
INFO (LIB-511): (define_leafcell): Leafcell 'N_18_MM' (instance) has been identified with pin_position (0 1 2 3) mapped to (D G S B).
LIBERATE parameter "extsim_exclusive" set to "1"
INFO (LIB-511): (define_leafcell): Leafcell 'P_18_MM' (instance) has been identified with pin_position (0 1 2 3) mapped to (D G S B).
LIBERATE parameter "simulator" set to "spectre"
LIBERATE parameter "char_library_skip_var_list" set to ""
Start Characterizing Library at (Wed May 19 00:36:13 IST 2021)

WARNING (LIB-909): (read_spice): Could not find a model/subckt definition for instance 'c' named 'mim_va' with '2' terminals.  Liberate will attempt to guess the device type. Read the models in read_spice or use define_leafcell to map the name to a model/subckt and rerun.
WARNING (LIB-909): (read_spice): Could not find a model/subckt definition for instance 'r1' named 'res_va' with '2' terminals.  Liberate will attempt to guess the device type. Read the models in read_spice or use define_leafcell to map the name to a model/subckt and rerun.
WARNING (LIB-909): (read_spice): Could not find a model/subckt definition for instance 'rs' named 'reshr_va' with '2' terminals.  Liberate will attempt to guess the device type. Read the models in read_spice or use define_leafcell to map the name to a model/subckt and rerun.
WARNING (LIB-909): (read_spice): Could not find a model/subckt definition for instance 'rs' named 'resnp_va' with '2' terminals.  Liberate will attempt to guess the device type. Read the models in read_spice or use define_leafcell to map the name to a model/subckt and rerun.
WARNING (LIB-909): (read_spice): Could not find a model/subckt definition for instance 'rs' named 'respp_va' with '2' terminals.  Liberate will attempt to guess the device type. Read the models in read_spice or use define_leafcell to map the name to a model/subckt and rerun.
WARNING (LIB-933): To enable automatic leaf-cell recognition, the variable 'extsim_model_include' is required.
INFO (LIB-956): (read_spice): Reading file: 'dut.scs'.
INFO (LIB-955): (read_spice): Further occurrences of the preceding message will be suppressed.
INFO (LIB-940): The parser has identified the following leaf cells. Review these for missing or incorrect settings and if needed, add them to your Tcl script and rerun.
INFO (LIB-906): (AUTO): define_leafcell -type black_box -pin_position {0 1 2} l_slcr20k_rf
INFO (LIB-906): (AUTO): define_leafcell -type c -pin_position {0 1 2} mimcapm_rf
INFO (LIB-906): (AUTO): define_leafcell -type c -pin_position {0 1} mimcaps_mm
INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1 2 3} n_l18w500_18_rf
INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1 2 3} n_l34w500_33_rf
INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1 2 3} n_po7w500_18_rf
INFO (LIB-906): (AUTO): define_leafcell -type nmos -pin_position {0 1 2 3} n_po7w500_33_rf
INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1 2 3} p_l18w500_18_rf
INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1 2 3} p_l34w500_33_rf
INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1 2 3} p_po7w500_18_rf
INFO (LIB-906): (AUTO): define_leafcell -type pmos -pin_position {0 1 2 3} p_po7w500_33_rf
INFO (LIB-906): (AUTO): define_leafcell -type diode -pin_position {0 1} vardiop_rf
INFO (LIB-906): (AUTO): define_leafcell -type black_box -pin_position {0 1 2} varmis_18_rf
INFO (LIB-907): (AUTO): define_leafcell -element -type c -pin_position {0 1} mim_va
INFO (LIB-943): Finished reading netlist(s) at May 19 00:36:13.
INFO (LIB-711): Feature 'Virtuoso_Multi_mode_Simulation' exists in the license pool. The parameter 'spectre_use_mmsim_token_license' will be set to '1'.
INFO (LIB-1008): (char_library): This LIBERATE release was qualified with MMSIM version '' but newer version '19.1.0.396.isr8' was detected. If MMSIM-related issues are found, update to the qualified MMSIM version and re-run.
INFO (LIB-966): Using Spectre version 19.1.0.396.isr8 located at: /home/installs/SPECTRE191/tools/bin/spectre.
*Info* Use temporary directory '/home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate'.
LIBERATE parameter "extsim_deck_dir" defaulted to cad19:/home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/decks.cad19.T20210519003610741304S0014229
*Error* (char_library) : set_var extsim_use_leaf_cell is enabled, but
 not all leaf_cells have -extsim_model parameter defined. Since set_var extsim_model_include
 is not used.  Cannot continue, exiting.
*Note* : The following cells do not have -extsim_model parameter specified in define_leafcell command.
      : N_18_MM
      : P_18_MM

Peak memory usage:          340 MB
Peak virtual memory usage:  303 MB
Peak physical memory usage: 37 MB
Wall time      :    0.00 hours (3.00 seconds)
LIBERATE exited on cad19 at Wed May 19 00:36:13 2021

My char.tcl file is as follows:

define_template -type delay -index_1 {61.75 158.9 794.1} -index_2 {18.732 37.464 74.928} delay_3x3
define_template -type power -index_1 {61.75 158.9 794.1} -index_2 {18.732 37.464 74.928} power_3x3
define_template -type constraint -index_1 {61.75 158.9 794.1} -index_2 {18.732 37.464 74.928} constraint_3x3

set model "/home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/Models/Spectre/core_rf_v2d4.lib.scs"

set_operating_condition -voltage 0.3 -temp 25

set_var extsim_model_include \$model

define_leafcell -type nmos -pin_position {0 1 2 3} N_18_MM
define_leafcell -type pmos -pin_position {0 1 2 3} P_18_MM

read_spice -format spectre {dut.scs}

define_cell \
-input {in} \
-output {out} \
-delay delay_3x3 \
-power power_3x3 \
-constraint constraint_3x3 \
{INVX1}

define_cell \
-input {a b} \
-output {y} \
-delay delay_3x3 \
-power power_3x3 \
-constraint constraint_3x3 \
{NAND2X1 NOR2X1 AND2X1 OR2X1 XOR2X1 XNOR2X1}

char_library -extsim spectre
write_ldb lowpower.ldb
write_library lowpower.lib

I am using UMC's 180nm FDK and the MOS devices are named as N_18_MM and P_18_MM for nMOS and pMOS respectively.

I have a feeling that there's something wrong with my .tcl file

How do I go about this?

Thanks in advance!

  • Guangjun Cao
    in reply to iamKarthikBK
    iamKarthikBK said:
    *Warning* (char_library) : Cell 'OR2X1' has transistors (eg. MavD28_1_unmatched) with floating bulk(s). Bulk nodes should either be connected to supplies or driven by other active devices. Simulation results can be very inaccurate.

    first, make sure this warning is solved. you may have a netlist issue.

    iamKarthikBK said:
    I don't see sim_duration in the reference manual

    It is definitely documented.

    you might also need to increase init_delay_period for clock to be larger than your maximum delay+transition, in order for the tool to correctly estimate the transient simulation time for final run.

    iamKarthikBK said:
    ERROR (LIB-54): Some output transitions did not cross both 'measure_slew_*' thresholds for arc of cell:'AND2X1', r_pin:'a', r_pin dir:'r', pin:'y', pin dir:'r', type:'combinational rise_transition'. To debug, save and review the simulation results for deck: delay_1 using extsim_save_passed and extsim_save_failed.

    follow this suggestion to save the failed decks. then, go to the extsim_deck_dir-->untar the file, cellname/map.list indicats the directory for each arc/deck. open the sim.sp for the failed arc, remove save**none if exists. run spectre on this sim.sp and check the waveform. if the transition does not reach the VDD/VSS, increase the simulation time (.tran comman). if this solves the incomplete transition, increase the sim_duration and init_delay_period (for clock pin). DO NOT USE sim_estimate_duration=0, IT MAY CAUSE INCORRECTLY LARGE POWER.

  • iamKarthikBK
    in reply to Guangjun Cao
    Guangjun Cao said:
    first, make sure this warning is solved. you may have a netlist issue.

    Ah, okay. This is the LVS error I reached out to imec for. I don't know how to fix this, I'll have to wait for them to get back to me.

    Guangjun Cao said:
    you might also need to increase init_delay_period for clock to be larger than your maximum delay+transition, in order for the tool to correctly estimate the transient simulation time for final run.

    Okay, I'll check this out.

    Guangjun Cao said:
    if the transition does not reach the VDD/VSS, increase the simulation time (.tran comman). if this solves the incomplete transition, increase the sim_duration and init_delay_period (for clock pin)

    Okay, I'll try to do this as soon as the LVS errors are fixed.

    Guangjun Cao said:
    DO NOT USE sim_estimate_duration=0, IT MAY CAUSE INCORRECTLY LARGE POWER.

    Noted!

    Thanks

  • Guangjun Cao
    in reply to iamKarthikBK

    iamKarthikBK said:

    Guangjun Cao said:
    first, make sure this warning is solved. you may have a netlist issue.

    Ah, okay. This is the LVS error I reached out to imec for. I don't know how to fix this, I'll have to wait for them to get back to me.

    If this device is in a well or isolated, you probably missed a well tap. adding a substrate contact and connecting it to the right net might solve it. The PCell normally has options to add a substrate contact. For a quick test in liberate, you may also hack the netlist, change the bulk connection to VDD or VSS net depending on the type of devices, ie. VDD net for nfet, VSS net for pfet. the terminal order is normally 'D G S B' 

  • iamKarthikBK
    in reply to Guangjun Cao
    Guangjun Cao said:
    If this device is in a well or isolated, you probably missed a well tap. adding a substrate contact and connecting it to the right net might solve it.

    Okay! I'll double-check that and get back :)

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